TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 301
TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
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9.3
Block diagram
DMA requested
(Request No. [15]
DMA
(Request No.[15]
Table 9-3 DMA request number chart
[0])
[0])
request No.
DMA
Burst requested
Single requested
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
CPU Data
Figure 9-1 DMAC Block Diagram
SIO10 Reception / Transmission
SIO11 Reception / Transmission
response
SIO1 Reception / Transmission
SIO2 Reception / Transmission
SIO3 Reception / Transmission
SIO4 Reception / Transmission
SIO5 Reception / Transmission
SIO6 Reception / Transmission
SIO7 Reception / Transmission
SIO8 Reception / Transmission
SIO9 Reception / Transmission
SIO0 Reception/Transmission
request
slave
AHB
DMA
I/F
and
I/F
AD Conversion End
SSP Transmission
SSP Reception
Burst
Page 277
−
Corresponding peripheral
Channel
register
register
Control
logic
logic
and
and
SSP Reception
master
Interrupt
AHB
request
I/F
Single
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
channel 0,1
TMPM362F10FG
AHB
DMACINTERR
DMACINTTC
DMACCLR[15:0]
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