TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 316
TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
- Current page: 316 of 744
- Download datasheet (8Mb)
9.4
Description of Registers
9.4.14
31-0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
channel (DMACxCConfiguration<E>="0") before change.
DestAddr[31:0]
Do not update DMACxCDestAddr during transfer. To change DMACxCDestAddr, be sure to disable the
Bit Symbol
DMACCxDestAddr (DMAC Channelx Destination Address Register)
31
23
15
0
0
0
7
0
R/W
Type
30
22
14
0
0
0
6
0
Sets a DMA transfer source address.
Confirm the transfer destination of memory, the bit width of IP and addresses before setting the DMA transfer.
Depending on the bit width of transfer destinations, the following restrictions are given.
000 :BYTE (8bits)
001 :Half-word (16bits)
010 :WORD (32bits)
Bit width of transfer destination
DMACCxControl<Dwidth[2:0]>
29
21
13
0
0
0
5
0
Page 292
28
20
12
0
0
0
4
0
DestAddr
DestAddr
DestAddr
DestAddr
No restrictions
Set the number by a factor of two
(0x00,0x02,0x04,0x06,0x08,0x0A,0x0C…)
Set the number by a factor of four (0x00,0x04,0x08,0x0C…)
Description
27
19
11
0
0
0
3
0
Setting of LSB address
26
18
10
0
0
0
2
0
25
17
0
0
9
0
1
0
TMPM362F10FG
24
16
0
0
8
0
0
0
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