TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 535
TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
- Current page: 535 of 744
- Download datasheet (8Mb)
<CECACKDIS>
CECRCR1
Transmission
Reception
(6)
imately 1.526 ms. The start time of outputting "Low" is specified with CECRCR1<CECLNC> bit
that sets the noise cancelling time.
cle error, buffer overrun and waveform error) is suspended or not. Setting "1" generates no interrupt
at the error detection.
quent bits are interrupted, it is determined as a timeout, based on the setting in <CECTOUT> of the
CECRCR1 register.
The following describes the ACK response timing.
When the falling edge of the ACK bit from the initiator is detected, this IP outputs "Low" for approx-
Configure the CECRCR1 <CECRIHLD> bit to specify if a receive error interrupt (maximum cy-
If data continues to the ACK bit, an ACK response is executed by a reversed logic. If the subse-
After the ACK response or the timeout determination, an interrupt is generated.
Note:Use <CECLNC> in the same settings used for CECTCR<CECDTRS>.
Register setting
Receive Error Interrupt Suspend
(not responding logical "0")
(responding logical "0")
(0ms to approx. 0.092ms)
"0"
"1"
<CECLNC>
0/fs - 3/fs
0.6±0.2 ms
Conformity
Yes
Page 511
Header block address
(approx.1.526ms)
50/fs
Discrepancy
No
Conformity
Yes
No
Data block address
Discrepancy
TMPM362F10FG
No
No
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