TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 574
TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
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17.3
Operations
17.3
17.3.1
17.3.2
Operations
Detecting time can be selected between 2
ing time as specified is elapsed, the watchdog timer interrupt (INTWDT) generates, and the watchdog timer
out pin (WDTOUT) output "Low".
of the watchdog timer should be cleared by software instruction before INTWDT interrupt generates. If the bi-
nary counter is not cleared, the non-maskable interrupt generates by INTWDT. Thus CPU detects malfunc-
tion (runway), malfunction countermeasure program is performed to return to the normal operation.
the watchdog timer out pin to reset pins of peripheral devices.
low modes, the watchdog timer should be disabled.
The Watchdog timer is consists of the binary counters that work using the system clock (fsys) as an input.
To detect malfunctions (runaways) of the CPU caused by noise or other disturbances, the binary counter
Additionally, it is possible to resolve the problem of a malfunction (runaway) of the CPU by connecting
The watchdog timer begins operation immediately after a reset is cleared.
If not using the watchdog timer, it should be disabled.
The watchdog timer cannot be used as the high-speed frequency clock is stopped. Before transition to be-
In IDLE mode, its operation depends on the WDMOD <I2WDT> setting.
Also, the binary counter is automatically stopped during debug mode.
Basic Operation
Operation Mode and Status
-
-
-
-
-
STOP mode
SLEEP mode
SLOW mode
BACKUP STOP mode
BACKUP SLEEP mode
15
, 2
Page 550
17
, 2
19
, 2
21
, 2
23
and 2
25
by the WDMOD<WDTP[2:0]>. The detect-
TMPM362F10FG
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