TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 66
TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
- Current page: 66 of 744
- Download datasheet (8Mb)
6.3
Clock control
6.3.3
Starts oscillation after reset
Starts oscillation after reset
XT1
XT2
X1
X2
Clock system Diagram
Figure 6-1 shows the clock system diagram.
The input clocks selector shown with an arrow are set as default after reset.
High-speed
oscillation
Low-speed
oscillation
fperiph
CGOSCCR<WUPT[11:0]><WUPTL[1:0]>
CGOSCCR
CGOSCCR
fsys
<XTEN>
fs
<XEN>
CGOSCCR<WUEON>
warming-up timer
1/2
fs
fosc
1/4
1/8
CGOSCCR<PLLON>
Stops after releasing reset
CGOSCCR
<WUPSEL>
1/32
PLL
Figure 6-1 Clock Block Diagram
1/16
fpll = fosc×4
CGPLLSEL
1/32
<PLLSEL>
1/2
= fosc×8
CGSYSCR
<PRCK[2:0]>
fc
Page 42
1/2
CGSYSCR
<FPSEL1>
CGOSCCR<FCSTOP>
Operation after reset
1/4
FCSTOP
1/8
φT0
<SCOSEL[1:0]>
<GEAR[2:0]>
CGSYSCR
CGSYSCR
CGSYSCR<FPSEL0>
fgear
CGCKSEL
<SYSCK>
SCOUT
Systick Timer input
Peripheral I/O prescaler input
AHB-Bus I/O
APB-Bus I/O
SSP
IO-Bus I/O
RTC
CEC, RMC
CPU(STCLK)
TMRB, SIO
CPU(HCLK/FCLK),
ROM, RAM, SMC,
DMAC,BOOT ROM
TMRB, WDT, RTC,
SIO, SBI, CEC,
RMC, ADC, PORT
Sec. counter
Sampling clock
fperiph
(
fsys
fs
ADC conversion
clock <ADCLK>
TMPM362F10FG
I/O )
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