TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 674

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

22.2
Operation Mode
22.2.10.1
See Table 22-6 for the transfer format of this command.
RAM Transfer Command
1. The 1st byte specifies which one of the two serial operation modes is used. For a detailed descrip-
2. The 2nd byte, transmitted from the target board to the controller, is an acknowledge response
tion of how the serial operation mode is determined, see "22.2.10.6 Determination of a Serial Op-
eration Mode" described later. If the mode is determined as UART mode, the boot program
checks if the baud rate setting can be performed. During the first-byte processing, receiving op-
eration is prohibited. (SC4MOD0<RXE>=0)
to the 1st byte where the serial operation mode is set. When 1st byte is determined as UART
and can be set at the specified baud rate, data "0x86" is transmitted. When 1st byte is deter-
mined as I/O interface, data "0x30" is transmitted.
・ To communicate in UART mode
・ To communicate in I/O Interface mode
・ UART mode
・ I/O Interface mode
at the specified baud rate by setting UART. If the serial operation mode is determined as
UART, then the boot program checks if the baud rate setting can be performed. If that
baud rate cannot be set, the boot program aborts and any subsequent communications can-
not be done. Please refer to "Baud rate setting" for the method of judging whether the set-
ting of the baud rate is possible.
at 1/16 of the desired baud rate by the synchronous setting. Same as the 1st byte, a 1/16
of the specified baud rate is used in the 2nd transmission. From the 3rd byte (operation com-
mand data), users can transmit data at specified baud rate.
itors the level of I/O port. If the baud rate is high or operation frequency is high, CPU
may not distinguish the level of I/O port. To avoid this situation, the baud rate is set at
the 1/16 of desired baud rate in the I/O interface. When the serial operation mode is deter-
mined as I/O Interface mode, SCLK Input mode is set. The controller must ensure that
its AC timing restrictions are satisfied at the selected baud rate. In the case of I/O Inter-
face mode, the boot program does not check the receive error flag; thus there is no error ac-
knowledge responce (bit 3, 0x08).
rate can be set, a value of SC4BRCE is renewed and data "0x86" is sent to the control-
ler. If the baud rate cannot be set, transmit operation is stopped and no data is transmit-
ted. After transmission of 1st byte completed, the controller allows for five seconds of
time-out. If it does not receive 0x86 within the allowed time-out period, the controller
should give up the communication. Receiving operation is permitted by setting
SC4MOD0<RXE>=1, before loading 0x86 to the SIO transmit buffer.
the the I/O Interface mode and writes 0x30 to the SC4BUF. Then, the SIO4 waits for
the SCLK4 signal to come from the controller. After the transmission of the 1st byte com-
pleted, the controller should send the SCLK clock to the target board after a certain idle
time (several microseconds). This must be done at 1/16 of the desired baud rate. If the
2nd byte, which is from the target board to the controller, is 0x30, then the controller re-
gards it as communication possible. From the 3rd byte, users can transmit data at speci-
fied baud rate. Receiving operation is permitted by setting SC4MOD0<RXE>=1, before
loading 0x86 to the SIO.
The 1st byte is set to "0x86" and is transmitted from the controller to the target board
The 1st byte is set to "0x30" and is transmitted from the controller to the target board
In I/O interface mode, CPU considers the reception terminal to be an input port and mon-
The 2nd byte is used for distinguishing whether the baud rate can be set. If the baud
The boot program sets a value of the SC4MOD0 and SC4CR registers to configure
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TMPM362F10FG