TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 724
TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
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25.6
AC Electrical Characteristics
25.6.3
25.6.3.1
OUTPUT DATA
INPUT DATA
(Outout mode/
SCLK Clock High width (input)
SCLK Clock Low width (input)
SCLK cycle
Output Data ←
SCLK rise / fall (Note1)
SCLK rise →
Output Data hold / fall (Note1)
Valid Data input ←
SCLK rise / fall (Note1)
SCLK rise →
Input Data hold / fall (Note1)
SCLK cycle (programmable)
Output Data ← SCLK rise
SCLK rise → Output Data hold
Valid Data input ← SCLK rise
SCLK rise → Input Data hold
fsys cycle time. It varies depending on the programming of the clock gear function.
Serial Interface (SIO/UART)
(1)
(2)
In the table below, the letter x represents the SIO operation clock cycle time which is identical to the
Input rise
(Input fall
I/O Interface mode
mode)
mode)
SCLK
SCLK
RxD
TxD
Note 1: SCLK rising edge / falling edge …Measured relative to the programmed active edge of SCLK.
Note 2: Keep this value positive by adjusting SCLK cycle.
SCLK Input mode
SCLK output mode
Parameter
Parameter
t
t
SRD
OSS
VALID
0
t
0
Symbol
Symbol
SCY
t
t
t
t
t
t
t
t
t
t
t
t
OHS
OHS
SCH
SCL
SCY
OSS
SRD
HSR
SCY
OSS
SRD
HSR
Page 700
t
SCY
t
t
t
SCH
SCY
SCY
/2 − 3x− 45
t
x + 30
SCY
Min
Min
/2 − 20
/2 − 20
4x
4x
30
4x
45
VALID
0
+ t
1
/2
Equation
Equation
1
SCL
t
SCH
t
HSR
t
OHS
Max
Max
−
−
−
−
−
−
−
−
−
−
−
−
t
SCL
VALID
2
2
−29.4
62.5
62.5
(íç2)
62.5
45.6
62.5
11.3
11.3
125
Min
Min
fsys = 64 MHz
fsys = 64 MHz
30
45
0
Max
Max
−
−
−
−
−
−
−
−
−
−
−
−
VALID
3
TMPM362F10FG
3
Unit
Unit
ns
ns
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