TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 88
TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
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7.1
Overview
Note:
<PRI_n> bit is defined as a 3-bit configuration with this product.
Table 7-2 Priority grouping setting
(3)
<PRIGROUP[2:0]>
setting
Note:If the configuration of <PRI_n> is less than 8 bits, the lower bit is "0". For the exam-
Priority setting
000
001
010
011
100
101
110
111
・ Priority level
・ Priority grouping
ple, in the case of 3-bit configuration, the priority is set as <PRI_n[7:5]> and <PRI_n[4:0]
> is "00000".
are set to <PRI_n> bit in the system handler priority register.
the priority varies from 3 bits to 8 bits depending on products. Thus, the range of priority val-
ues you can specify is different depending on products.
255. The highest priority is "0". If multiple elements with the same priority exist, the small-
er the number, the higher the priority becomes.
tion interrupt and reset control register, <PRI_n> can be divided into the pre-emption prior-
ity and the sub priority.
emption priority, then it is compared with the sub priority. If the sub priority is the same
as the priority, the smaller the exception number, the higher the priority.
ority in the table are the number in the case that <PRI_n> is defined as an 8-bit configuration.
The external interrupt priority is set to the interrupt priority register and other exceptions
The configuration <PRI_n> can be changed, and the number of bits required for setting
In the case of 8-bit configuration, the priority can be configured in the range from 0 to
The priority group can be split into groups. By setting the <PRIGROUP> of the applica-
A priority is compared with the pre-emption priority. If the priority is the same as the pre-
The Table 7-2 shows the priority group setting. The pre-emption priority and the sub pri-
Pre-emption
None
[7:1]
[7:2]
[7:3]
[7:4]
[7:5]
[7:6]
field
[7]
<PRI_n[7:0]>
Subpriority
field
[1:0]
[2:0]
[3:0]
[4:0]
[5:0]
[6:0]
[7:0]
[0]
Page 64
pre-emption
Number of
priorities
128
64
32
16
8
4
2
1
subpriorities
Number of
128
256
16
32
64
2
4
8
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