MCIMX31LCVMN4C Freescale Semiconductor, MCIMX31LCVMN4C Datasheet - Page 47

• Manufacturer Part Number: MCIMX31LCVMN4C
• Description: IC MPU MAP I.MX31L 473-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX31r

Specifications of MCIMX31LCVMN4C

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: 1-Wire, ATA, EBI/EMI, FIR, I²C, MMC/SD, PCMCIA, SIM, SPI, SSI, UART/USART, USB, USB OTG
• Peripherals: DMA, LCD, POR, PWM, WDT
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.22 V ~ 3.3 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 473-MAPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Freescale Semiconductor
1
SD17
SD18
SD19
SD20
Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703.
ID
DQM (output)
DQS (output)
DQ (output)
DQ & DQM hold time to DQS
DQ & DQM setup time to DQS
Write cycle DQS falling edge to SDCLK output delay time.
Write cycle DQS falling edge to SDCLK output hold time.
SDCLK
SDCLK
SDRAM CLK and DQS related parameters are being measured from the
50% point—that is, high is defined as 50% of signal value and low is
defined as 50% of signal value.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is,
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
Table 35. Mobile DDR SDRAM Write Cycle Timing Parameters
Figure 37. Mobile DDR SDRAM Write Cycle Timing Diagram
SD17
Table 35
SD17
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
Parameter
Data
DM
indicates SDRAM requirements. All output signals
SD18
SD18
Data
DM
NOTE
NOTE
Data
SD17
DM
SD17
Data
DM
SD18
SD18
Data
DM
Symbol
tDSS
tDSH
tDH
tDS
Data
DM
SD19
1
Electrical Characteristics
0.95
0.95
Data
DM
Min
1.8
1.8
SD20
Max
—
—
—
—
Data
DM
Unit
ns
ns
ns
ns
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