MCIMX31LVKN5 Freescale Semiconductor, MCIMX31LVKN5 Datasheet - Page 37

• Manufacturer Part Number: MCIMX31LVKN5
• Description: IC MPU MAP I.MX31L 457-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX31r

Specifications of MCIMX31LVKN5

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, ATA, EBI/EMI, FIR, I²C, MMC/SD, PCMCIA, SIM, SPI, SSI, UART/USART, USB, USB OTG
• Peripherals: DMA, LCD, POR, PWM, WDT
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.22 V ~ 3.3 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 457-MAPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4.3.8
The three PLL’s of the MCIMX31 (MCU, USB, and Serial PLL) are all based on same DPLL design. The
characteristics provided herein apply to all of them, except where noted explicitly. The PLL characteristics
are provided based on measurements done for both sources—external clock source (CKIH), and FPM
(Frequency Pre-Multiplier) source.
4.3.8.1
Table 31
Freescale Semiconductor
1
CKIH frequency
CKIL frequency
(Frequency Pre-multiplier (FPM) enable mode)
Predivision factor (PD bits)
PLL reference frequency range after Predivider
PLL output frequency range:
Maximum allowed reference clock phase noise.
Frequency lock time
(FOL mode or non-integer MF)
SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
CS10
CS11
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
CS9
ID
lists the DPLL specification.
DPLL Electrical Specifications
SCLK Cycle Time
Data Out Hold Time
Data In Hold Time
SCLK High or Low Time
SCLK Rise or Fall
SSx pulse width
SSx Lead Time (CS setup time)
SSx Lag Time (CS hold time)
Data Out Setup Time
Data In Setup Time
SPI_RDY Setup Time
Electrical Specifications
Parameter
MPLL and SPLL
1
Parameter
Table 30. CSPI Interface Timing Parameters
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
UPLL
Table 31. DPLL Specifications
Min
190
15
15
52
—
—
—
1
32; 32.768, 38.4
Typ
26
—
—
—
—
—
1
t
Symbol
RISE/FALL
t
t
t
t
t
t
t
Smosi
Hmosi
Smiso
Hmiso
CSLH
t
SRDY
t
SCS
HCS
t
SW
clk
±
Max
75
532
240
398
16
35
—
100
2
MHz
MHz 15 ≤ CKIH frequency/PD ≤ 35 MHz
MHz
Unit
kHz FPM lock time ≈ 480 µs.
—
ps
—
Min
15 ≤ FPM output/PD ≤ 35 MHz
Cycles of divided reference clock.
60
30
25
25
25
—
—
5
5
6
5
Electrical Characteristics
Comments
Max
7.6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
37