XR16M2550IL32-F Exar Corporation, XR16M2550IL32-F Datasheet - Page 12

• Manufacturer Part Number: XR16M2550IL32-F
• Description: IC UART FIFO 16B 1.8V DUAL 32QFN
• Manufacturer: Exar Corporation
• Type: Dual UART with 16-byte FIFOsr

Specifications of XR16M2550IL32-F

• Number Of Channels: 2, DUART
• Package / Case: 32-VFQFN Exposed Pad
• Features: *
• Fifo's: 16 Byte
• Voltage - Supply: 2.25 V ~ 3.6 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 16 Mbps
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 1.62 V
• Supply Current: 0.5 mA to 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 45 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.62 V to 3.63 V
• No. Of Channels: 2
• Uart Features: Two Independent UART Channels, Device Identification & Revision
• Supply Voltage Range: 1.62V To 3.63V
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Digital Ic Case Style: QFN
• No. Of Pins: 32
• Filter Terminals: SMD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1285

XR16M2550
HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X/4X
internal clock. A bit time is 16/8/4 clock periods (see DLD). The transmitter sends the start-bit followed by the
number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and
TSR are reported in the Line Status Register (LSR bit-5 and bit-6).
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its selected trigger level. The transmit empty interrupt is enabled by IER
bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty.
F
2.10
2.10.1
2.10.2
2.10.3
IGURE
6. T
Transmitter
Transmitter Operation in non-FIFO Mode
Transmitter Operation in FIFO Mode
Transmit Holding Register (THR) - Write Only
RANSMITTER
16X or 8X or 4X
O
( DLD[5:4] )
PERATION IN NON
Clock
Data
Byte
Transmit Shift Register (TSR)
-FIFO M
Transmit
Register
Holding
(THR)
ODE
12
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
S
B
M
L
S
B
TXNOFIFO1
REV. 1.0.2