XR16M2550IL32-F Exar Corporation, XR16M2550IL32-F Datasheet - Page 25

• Manufacturer Part Number: XR16M2550IL32-F
• Description: IC UART FIFO 16B 1.8V DUAL 32QFN
• Manufacturer: Exar Corporation
• Type: Dual UART with 16-byte FIFOsr

Specifications of XR16M2550IL32-F

• Number Of Channels: 2, DUART
• Package / Case: 32-VFQFN Exposed Pad
• Features: *
• Fifo's: 16 Byte
• Voltage - Supply: 2.25 V ~ 3.6 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 16 Mbps
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 1.62 V
• Supply Current: 0.5 mA to 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 45 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.62 V to 3.63 V
• No. Of Channels: 2
• Uart Features: Two Independent UART Channels, Device Identification & Revision
• Supply Voltage Range: 1.62V To 3.63V
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Digital Ic Case Style: QFN
• No. Of Pins: 32
• Filter Terminals: SMD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1285

REV. 1.0.2
IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
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IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
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The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table,
associated with each of these interrupt levels.
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4.4
4.4.1
4.4.2
Logic 0 = Disable the RTS# interrupt (default).
Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from low to high.
Logic 0 = Disable the CTS# interrupt (default).
Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
low to high.
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
TXRDY is by TX trigger level or TX FIFO empty.
MSR is by any of the MSR bits 0, 1, 2 and 3.
Receive Xoff/Special character is by detection of a Xoff or Special character.
CTS# is when its transmitter toggles the input pin (from LOW to HIGH) during auto CTS flow control.
RTS# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS flow control.
LSR interrupt is cleared by a read to the LSR register.
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading RHR.
TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
MSR interrupt is cleared by a read to the MSR register.
Xoff interrupt is cleared by a read to ISR or when Xon character(s) is received.
Special character interrupt is cleared by a read to ISR or after the next character is received.
RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.
Interrupt Status Register (ISR) - Read-Only
Interrupt Generation:
Interrupt Clearing:
Table
10, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO
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XR16M2550