XR88C681J-F Exar Corporation, XR88C681J-F Datasheet - Page 45

• Manufacturer Part Number: XR88C681J-F
• Description: IC UART CMOS DUAL 44PLCC
• Manufacturer: Exar Corporation
• Type: CMOS Dual Channel UARTr

Specifications of XR88C681J-F

• Number Of Channels: 2, DUART
• Package / Case: 44-LCC (J-Lead)
• Features: *
• Fifo's: 1 Byte, 3 Byte
• Voltage - Supply: 5V
• With Parallel Port: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 1 Mbps
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current: 15 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• Propagation Delay Time Ns: 400 ns
• No. Of Channels: 2
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 44
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1329

-
of the CPU to be asserted. Once the CPU has completed
its current instruction, the CPU Module will assert the
-
Acknowledge) input to the DUART. The purpose of the
asserted
very next cycle will be an “IACK” or “Interrupt
Note: The LSB of the IVR is always set to “0” once read by the CPU. Interrupt Service Routines must begin at even ddresses.
Additionally, the user must be aware of the contents that he/she loads into the I Register of the CPU, during run time.
INTR output. This action will, in turn, cause the
INTA signal. This will in turn assert the
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Rev. 2.11
Table 13. The Relationship between the Contents of the Interrupt Vector Register (of the DUART)
-
Contents of the I Register (within the CPU)
IACK signal is to inform the DUART that the
Figure 19. Schematic of an Approach to Interface the DUART to the Z-80
Most Significant Byte
Z80 CPU
A0 - A15
D0 - D7
-MREQ
-IORQ
and the location of the Interrupt Service Routine (Z-80 CPU)
-INT
-WR
M1
-RD
-
IACK (Interrupt
CPU (for Z-Mode Operation)
Bit 9
-
INT input
Bit 8
Address
Decoder
Circuitry
45
The 7 Most Significant Bits within the Interrupt Vector
Bit 7
Acknowledge” cycle. DUART, in response to the
signal, will place the contents of the Interrupt Vector
Register (IVR) on the Data Bus. This data will be read by
the CPU, and program control will be branched to the
appropriate interrupt service routine. In the case of the
Z-80 CPU, this location is a 16 bit address which is
determined from Table 13.
-MEMW
-MEMR
-INTA
from Vcc or higher
priority peripheral
Bit 6
to lower priority
CS_DUART
A0 - A3
peripheral
Register of the DUART
Bit 5
Least Significant Byte
Bit 4
IEI
IEO
-CS
A0 - A3
D0 - D7
-INTR
-WR
-RD
-IACK
XR88C681
Bit 3
XR88C681
Bit 2
Bit 1
-
Bit 0
IACK
0