ST16C554DIJ68-F Exar Corporation, ST16C554DIJ68-F Datasheet
ST16C554DIJ68-F
Specifications of ST16C554DIJ68-F
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ST16C554DIJ68-F Summary of contents
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JUNE 2006 GENERAL DESCRIPTION The ST16C554/554D (554 quad Universal Asynchronous Receiver and Transmitter (UART) with 16 bytes of transmit and receive FIFOs, selectable receive FIFO trigger levels and data rates 1.5 Mbps. Each UART has ...
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... TQFP TXA 8 Intel Mode Only IOW# 9 TXB 10 CSB# 11 INTB 12 RTSB# 13 GND 14 DTRB# 15 CTSB# 16 ORDERING INFORMATION P N ART UMBER ST16C554CQ64 ST16C554DCQ64 ST16C554DIQ64 ST16C554DCJ68 ST16C554DIJ68 ST68C554CJ68 ST68C554IJ68 DSRA DSRD# CTSA CTSD# DTRA DTRD# VCC 13 57 GND RTSA RTSD# IRQ INTD CS# 16 ST16C554 ...
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REV. 4.0.1 PIN DESCRIPTIONS Pin Description 64-LQFP 68-PLCC N T AME YPE DATA BUS INTERFACE I ...
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ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO Pin Description 64-LQFP 68-PLCC N T AME YPE INTA (IRQ#) (OD) INTB INTC 37 49 INTD 43 55 (N.C.) ...
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REV. 4.0.1 Pin Description 64-LQFP 68-PLCC N T AME YPE DTRA DTRB DTRC DTRD DSRA DSRB DSRC DSRD# ...
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ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO 1.0 PRODUCT DESCRIPTION The ST16C554 (554) integrates the functions of 4 enhanced 16C550 Universal Asynchrounous Receiver and Transmitter (UART). Each UART is independently controlled and has its own set of device ...
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REV. 4.0.1 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The 554 data interface supports the Intel compatible types ...
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ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO 2.2 Device Reset The RESET input resets the internal registers and the serial interface outputs in all channels to their default state (see Table 13). An active high pulse of longer ...
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REV. 4.0.1 2.4 Channels A-D Internal Registers Each UART channel in the 554 has a set of enhanced registers for controlling, monitoring and data loading and unloading. The configuration register set is compatible to those already available in the standard ...
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ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO loading or unloading the FIFO in a block sequence determined by the programmed trigger level. The following table show their behavior. Also see T 5: TXRDY# RXRDY# O ABLE AND FCR ...
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REV. 4.0 IGURE AUD ATE ENERATOR Crystal XTAL1 Osc / XTAL2 Buffer ABLE YPICAL DATA RATES WITH A O Data Rate O Data Rate UTPUT UTPUT MCR Bit-7=1 MCR Bit-7 ...
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ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO 2.9.2 Transmitter Operation in non-FIFO Mode The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the data byte is ...
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REV. 4.0.1 2.10.1 Receive Holding Register (RHR) - Read-Only The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register. It provides the receive data interface to the host processor. The RHR ...
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ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO 2.11 Internal Loopback The 554 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular ...
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REV. 4.0.1 3.0 UART INTERNAL REGISTERS Each UART channel in the 554 has its own set of configuration registers selected by address lines A0, A1 and A2 with a specific channel selected (See and Table UART CHANNEL ...
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ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO T ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR Bit ...
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REV. 4.0.1 4.3.1 IER versus Receive FIFO Interrupt Mode Operation When the receive FIFO (FCR BIT and receive interrupts (IER BIT are enabled, the RHR interrupts (see ISR bits 2 and 3) status will reflect the ...
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ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO 4.4 Interrupt Status Register (ISR) The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. ...
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REV. 4.0.1 4.5 FIFO Control Register (FCR) - Write-Only This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger levels, and select the DMA mode. The DMA, and FIFO modes are defined as follows: ...
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ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO 4.6 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and ...
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REV. 4.0.1 LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format. • LCR BIT-5 = logic 0, parity is not forced (default). • LCR BIT-5 = logic 1 and LCR ...
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ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO MCR[3]: INT Output Enable Enable or disable INT outputs to become active or in three-state. This function is associated with the INTSEL input, see below table for details. This bit is ...
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REV. 4.0.1 LSR[4]: Receive Break Tag • Logic break condition (default). • Logic 1 = The receiver received a break signal (RX was LOW for at least one character frame time). In the FIFO mode, only one ...
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ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO MSR[4]: CTS Input Status A HIGH on the CTS# pin will stop UART transmitter as soon as the current character has finished transmission, and a LOW will resume data transmission. Normally ...
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REV. 4.0.1 T 13: UART RESET CONDITIONS FOR CHANNELS A-D ABLE REGISTERS DLM, DLL RHR THR IER FCR ISR LCR MCR LSR MSR SPR I/O SIGNALS TX IRTX RTS# DTR# RXRDY# TXRDY# INT (16 Mode) IRQ# (68 Mode) 2.97V TO ...
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ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (64-LQFP) Thermal Resistance (68-PLCC) ELECTRICAL CHARACTERISTICS DC ELECTRICAL ...
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REV. 4.0.1 AC ELECTRICAL CHARACTERISTICS +70 C (-40 + APPLICABLE S P YMBOL ARAMETER CLK External Clock Low/High Time OSC UART Crystal/External Clock Frequency T Address Setup Time (16 Mode) ...
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ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO AC ELECTRICAL CHARACTERISTICS +70 C (-40 + APPLICABLE S P YMBOL ARAMETER T Delay From IOR# To Reset Interrupt RRI T ...
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REV. 4.0 IGURE ODEM NPUT UTPUT ...
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ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO F 14 IGURE ODE NTEL ATA A0-A7 Valid Address T AS CS# IOW# D0- IGURE ODE OTOROLA A0-A7 Valid ...
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REV. 4.0 IGURE ODE OTOROLA A0-A7 Valid Address T ADS CS# T RWS R/W# D0- & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading ...
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ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO F 18 & I IGURE RANSMIT EADY NTERRUPT TX Start (Unloading) D0:D7 Bit IER[1] ISR is read enabled INT* T WRI T SRT TXRDY IOW# (Loading data ...
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REV. 4.0 & I IGURE ECEIVE EADY NTERRUPT Start Stop Bit Bit RX S D0:D7 S D0:D7 INT RX FIFO fills Trigger Level or RX Data Timeout RXRDY# IOR# (Reading data out of ...
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ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO F 22 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX S D0:D7 (Unloading) IER[1] ISR is read enabled INT* T WRI TXRDY# IOW# (Loading data ...
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REV. 4.0.1 PACKAGE DIMENSIONS 64 LEAD LOW-PROFILE QUAD FLAT PACK ( 1.4 mm LQFP) A Seating Plane Note: The control dimension is the millimeter column SYMBOL α 2.97V ...
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ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO 68 LEAD PLASTIC LEADED CHIP CARRIER (PLCC Note: The control dimension is the inch column SYMBOL ...
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... Corrected Part Numbers in Ordering Information. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...
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ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO GENERAL DESCRIPTION ................................................................................................ 1 F .................................................................................................................................................... 1 EATURES A ............................................................................................................................................... 1 PPLICATIONS F 1. ST16C554 B D IGURE LOCK IAGRAM ..................................................................................................................................................... 2 IGURE IN UT SSIGNMENT ...
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REV. 4.0.1 4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 24 4.11 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE................................................. 24 T 13: UART RESET CONDITIONS FOR CHANNELS A-D ................................................................................................. 25 ABLE ABSOLUTE MAXIMUM RATINGS ................................................................................. 26 TYPICAL PACKAGE ...