XR82C684CJ-F Exar Corporation, XR82C684CJ-F Datasheet
XR82C684CJ-F
Specifications of XR82C684CJ-F
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XR82C684CJ-F Summary of contents
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FEATURES GENERAL DESCRIPTION ORDERING INFORMATION Part No Operating Package Temperature Range XR82C684 • ...
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XR82C684 PRINCIPLES OF OPERATION Figure 1 Figure Figure 1. Block Diagram of the XR82C684 in the 68 Mode ...
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Figure 2. Block Diagram of the XR82C684 in the 88 Mode XR82C684 ...
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XR82C684 44 Pin PLCC 68 Pin PLCC ...
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PIN DESCRIPTION Pin # Pin # 68 Pin PLCC 44 Pin PLCC Symbol Type Power Supply Pin. Mode Select. Output Port 2 (General Purpose Output). Output 3 (Active low). Transmitter Serial Data Output (Channel B). Receiver Serial Data Input (Channel ...
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XR82C684 Pin # Pin # 68 Pin PLCC 44 Pin PLCC Symbol Type Output 6 (General Purpose Output). Output 7 (General Purpose Output). LSB of the Eight Bit Bi-Directional Data Bus. Bi-Directional Data Bus. Bi-Directional Data Bus. Bi-Directional Data Bus. ...
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Pin # Pin # 68 Pin PLCC 44 Pin PLCC Symbol Type Receiver Serial Data Input (Channel D). Transmitter Serial Data Output (Channel D). Data Transfer Acknowledge (Three-State, Active- Low). Interrupt Enable Output (Z Mode; Active High). Interrupt Acknowledge (Active ...
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XR82C684 Pin # Pin # 68 Pin PLCC 44 Pin PLCC Symbol Type Interrupt Request Output (Active Low, Open-Drain). Output 11 (General Purpose Output). Output 10 (General Purpose Output). Output 9 (General Purpose Output). Output 8 (General Purpose Output). Transmitter ...
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Pin # Pin # 68 Pin PLCC 44 Pin PLCC Symbol Type Interrupt Enable Input (Z-Mode; Active High). Note: if the user is operating this device in the “68 Mode” the “88 I-Mode,” then this pin should be ...
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XR82C684 Pin # Pin # 68 Pin PLCC 44 Pin PLCC Symbol Type Input 5 (General Purpose Input). Input 6 (General Purpose Input). Input 7 (General Purpose Input). Reveive Serial Data Input (Channel A). Transmitter Serial Data Output (Channel A). ...
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DC ELECTRICAL CHARACTERISTICS Test Conditions: Symbol Parameter Notes 1 Parameters are valid over the specified temperature and operating supply ranges. Typical values are 25C, V processing parameters. 2 All voltages are referenced to ground (GND). For testing, input signal ...
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XR82C684 AC ELECTRICAL CHARACTERISTICS Test Conditions: Symbol Parameter Reset Timing (See Figure 56) XR82C684 Read and Write Cycle Timing - 88 Mode (Figure 57) Z-Mode Interrupt Cycle Timing (Figure 58) XR82C684 Read, Write and Interrupt Cycle Timing -68 Mode ...
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AC ELECTRICAL CHARACTERISTICS Symbol Parameter XR82C684 Read, Write and Interrupt Cycle Timing -68 Mode (Figure 59, Figure 60 and Figure 61) (Cont’d) Port Timing - XR82C684 (Figure 62) Interrupt Output Timing - XR82C684 (Figure 63) Clock Timing (Figure 64) Transmitter ...
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XR82C684 AC ELECTRICAL CHARACTERISTICS Symbol Parameter Receiver Timing XR82C684 (Figure 66) Notes 1 Parameters are valid over the specified temperature and operating supply ranges. Typical values are 25C, V processing parameters. 2 All voltages are referenced to ground (GND). For ...
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SYSTEM DESCRIPTION A. DATA BUS BUFFER XR82C684 B. OPERATION CONTROL BLOCK 68 Mode Figure 3 88 Mode ...
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XR82C684 Figure 3. External Logic Circuitry Required To Interface a 6800 Family Processor to an “88-Mode” XR82C684 Device B.1 Quart Register Addressing Table 1 Please note that some of the registers are “Read Only” and others are “Write Only”. Each ...
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Read Mode Registers Address (Hex) Register Name Note: The shaded blocks are not Read/Write registers but are rather “Address-Triggered” Commands. Table 1. Quart Port And Register Addressing Write Mode Registers Symbol Register Name XR82C684 Symbol ...
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XR82C684 Table 1 the suffix “n” is used at the end of many of the QUART registers symbols in order to refer, generically, to any one of the four channels Bit 7 Bit 6 Bit 5 Miscellaneous Commands Bit 7 ...
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Bit 7 Bit 6 Bit 5 Bit 4 Table 2. Miscellaneous Commands, Upper Nibble of All Command Registers, Unless Otherwise Specified Description Start Break: Stop Break: Set Rx BRG Select Extend Bit: Clear Rx BRG Select Extend Bit: Set Tx ...
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XR82C684 Table Table 1 Please note that this “Read Operation” will not result in placing the contents of a QUART register on the data bus. The only thing that will happen, ...
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C.1 Interrupt Status Registers (ISR1 and ISR2) ISR1 Register Bit Format Bit 7 Bit 6 Bit 5 Input Port Delta Break RXRDY/ Change B FFULLB ISR2 Register Bit Format Bit 7 Bit 6 Bit 5 Input Port Delta Break RXRDY/ ...
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XR82C684 Note: If this bit is configured to reflect the FFULLB indicator, this bit will not be set (nor will produce an interrupt request) if one or two characters are still remaining in RHRB, following data reception. Hence ...
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Please note that in order to enable this Interrupt Condition, the user must do two things: 1. Write the appropriate data to the lower nibble of the Auxiliary Control Register, ACR2[3:0]. In this step, the user is specifying which ...
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XR82C684 Note: If this bit is configured to reflect the FFULLC indicator, this bit will not be set (nor will produce an interrupt request) if one or two characters are still remaining in RHRC, following data reception. Hence ...
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C.4 Interrupt Vector Registers, IVR1 and IVR2 C.5 Limitations of the QUART Interrupt Structure C.6 Servicing QUART Interrupts XR82C684 C.6.1 “68 Mode” Interrupt Servicing ...
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XR82C684 XR82C684 Figure 4. Simple Illustration Depicting the Interfacing of the XR82C684 QUART to a 68000 Processor Figure 5 Figure 4 MC68000 Processor ...
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Please note that the QUART does not requires that its -CS input be asserted in order to respond to an “Interrupt Acknowledge” cycle. QUART only requires that its -IACK input be asserted. MC68000 Figure 5. Detailed Schematics of the XR82C684 ...
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XR82C684 Figure 6. XR82C684/68000 CPU Interrupt Cycle Timing Figure 6 Interrupt Service Routine Section C.1 C.6.2 “88 Mode” Interrupt Servicing Section C.6.2.2 ...
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C.6.2.1 I-Mode Interrupt Servicing XR82C684 Direct Interrupt Processing • (External) Vectored Interrupt Processing Table 4 Table 4 Comments ...
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XR82C684 Type of Interrupt • P• /C Processing • • • • • Table 4. Summary of • P/• C and Their Types of Interrupt Processing (I - Mode) Table 4 C.6.2.2 8051 Microcontroller Comments • • • • • ...
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Figure 7. Block Diagram of the 8051 Microcontroller Figure 8. Pin Out of the 8051 Microcontroller XR82C684 • Port 0 (P0.0 - P0.7) Port 1 (P1.0 - P1.7) ...
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XR82C684 Port 2 (P2.0 - P2.7) Port 3: Table 5 Bit Name Alternate Function Table 5. Alternate Functions of Port 3 Pins ALE - Address Latch Enable -INT0 (P3.2) and -INT1 (P3.3) • Table 6 Interrupt Table 6. Interrupt Service ...
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CPU Figure 9. An Approach to Interfacing the XR82C684 QUART to the 8051 Microcontroller Figure 9 Figure 5 • C.6.2.3 8080A Microprocessor 74HC373 XR82C684 XR82C684 ...
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XR82C684 Figure 10 8224 Clock Generator Figure 10. Schematic of 8080A CPU Module 8080A CPU Module Interrupt Structure 8080A CPU 8228 System Controller Table 7 ...
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Op-Code (hex) Mnemonic Table 7. 8080A and 8085 CPU Restart Instructions Used with Vectored Interrupts Table 7 Interfacing the 8080 CPU Module to the XR82C684 QUART for Interrupt Processing Figure 11 Please note that Figure 11 only includes information pertaining ...
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XR82C684 8080A CPU Figure 11. Circuit Schematic depicting approach to Interface the XR82C684 QUART to the 8080A CPU, for “External” Vectored Interrupt Processing (Interrupt Service Routine resides at 0020 in Memory) C.6.2.4 8085 Microprocessor 8228 Bi-directional Bus Driver SN74LS244 Figure ...
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Figure 12 8085 CPU Figure 12. A Schematic of the 8085 CPU Module XR82C684 74LS373 ...
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XR82C684 8085 CPU Figure 13. Schematic of the XR82C684 Interface to the 8085 CPU Module (Memory Mapped) Figure 13 the XR82C684 QUART, in this case, is memory mapped (e.g., the signals -MEMR and -MEMW of the CPU module are connected ...
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Input Name Table 8. 8085 CPU Maskable Interrupt Request Inputs and their Features Direct Interrupts Table 8 Acknowledge Trigger Priority Type Signal? Table 8 Table 8 Section C.6.2.3 XR82C684 Address (Hex) Table 7 ...
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XR82C684 8085 CPU Figure 14. The XR82C684/8085 CPU Interface for Direct Interrupt Processing (Interrupt Service Routine is located at 0034 in system memory) Figure 14 Figure 15 74LS373 Figure 14 XR82C684 ...
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CPU Figure 15. The XR82C684/8085 CPU Interface for Vectored Interrupt Processing (Interrupt Service Routine is Located at 0020 Figure 15 C.6.2.5 68HC11 Microcontroller SN74LS244 74LS373 in System Memory XR82C684 XR82C684 ...
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XR82C684 Figure 16. Block Diagram of the MC68HC11 Microcontroller Figure 16 • Please note that this does not mean that there is 64K bytes of memory, or other addressable portions within the device. • Port A • Port B • ...
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Port D Port E -IRQ XR82C684 AS/STRA Figure 17. Figure 17 • • • • Figure 18. • • Figure 17. Figure 3. ...
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XR82C684 68HC11 Figure 17. XR82C684/MC68HC11 Microcontroller Interfacing Approach Figure 18. Glue Logic Circuitry Required to Interface the MC68HC11 • the XR82C684 QUART C.6.2.6 Z-80 CPU Section C.6.2.1 C.6.3 Z-Mode Interrupt Servicing 74HC373 Table 2 XR82C684 ...
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Figure 19. A Diagram of Numerous QUARTs configured in an Interrupt Daisy Chain (for Z-Mode Operation) IEI - Interrupt Enable Input Note: those interrupts which have been masked out by the IMR are still disabled. However, if this ...
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XR82C684 Figure 20. Timing Diagram Illustrating the Sequence of Events occurring between the QUART and the CPU during an Interrupt Request/Acknowledge and Servicing Additional Notes About Z-Mode Operation Figure 19 Figure 20 Figure 20 ...
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Please note that it is possible to interface the 80X86 Family of microprocessors to an I-Mode QUART, however, additional components and design complexity would be required in order to accomplish this C.6.3.1 Z-80 ...
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XR82C684 External Vectored Interrupt Processing (Interrupt Mode 0) • Op-Code (hex) Mnemonic Table 9. Z-80 CPU Restart Instructions Used with Vectored Interrupts (Mode 0) Table 9 Section C.6.2.3 Direct Interrupt Processing (Interrupt Mode 1) • Table 9 Restart Address (hex) ...
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Most Significant Byte Bit Bit Bit Bit Bit Table 10. The Relationship Between the Contents of the Interrupt Vector Registers (of the QUART) and the Location of the Interrupt Service Routine (Z-80 CPU) Note: The ...
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XR82C684 C.6.3.2 8086 Microprocessor Please note that in this figure, pins have some additional labels, located off to the right of the package. These additional labels will be explained later in this text. Table 11 • 8086 ...
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CPU Figure 25. Schematic of the 8086 CPU Mode (Min Mode) XR82C684 74LS373 74LS373 ...
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XR82C684 8086 CPU Figure 26. Schematic of the 8086 CPU Mode (Max Mode) 8086 • C Interrupt Processing • 8288 Bus Controller 74LS373 74LS373 Figure 27 Please note that the QUART has been configured to operate in the Z-Mode. Therefore, ...
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CPU Figure 27. Schematic of the XR82C684 QUART Device Interfacing to a “Min” Mode 8086 CPU Device D. TIMING CONTROL BLOCK 74LS373 74LS373 Figure 28A XR82C684 XR82C684 Figure 28 ...
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XR82C684 Figure 28. Block Diagram of the Portion of the QUART Timing Control Block Which Services Channels A and B ...
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Figure 28A. Block Diagram of the Portion of the QUART Timing Control Block Which Services Figure 28 Figure 28A Please note that each “half” of the Timing Control Block consists of a 16-bit Counter/Timer, a Baud Rate Generator, a set ...
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XR82C684 Figure 29. Recommended Schematics for the XTAL Oscillator Circuitry Note: The user also has an option to drive the Oscillator Circuit with a TTL input signal, in lieu of using a crystal oscillator. If this approach is used, the ...
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D.2 Bit Rate Generator note that the BRGs will only generate these standard bit rates if the Oscillator Circuit is running at 3.6864 MHz (for the bit rates presented in Table 15) or running at 7.3728 MHz (for the bit ...
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XR82C684 Figure 31A. Block Diagram of the Bit Rate Generator portion of the Timing Control Block, for D.3 Counter/Timers Figure 32A Channels C and D and Counter/Timer mode, the Timing Source and ACR[6:4] for Counter/Timers #1 and #2, respectively. Figure ...
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Figure 32. A Block Diagram of the Circuitry Associated with Counter/Timer #1 Figure 32A. A Block Diagram of the Circuitry Associated with Counter/Timer #2 XR82C684 ...
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XR82C684 Bit Bit Bit C/T Timing Source Mode Note: The “shaded” options are only available in the 68 pin PLCC. Table 13. ACR1[6:4] Bit Field Definition - C/T#1 Bit Bit Bit C/T Timing Source ...
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D.3.2 COUNTER MODE Bit 7 Bit 6 Table 15 Table 14. Bit Format of the Clock Select Registers, CSRA and CSRB D.4 External Inputs can specify whether a clock signal, applied to one of these external inputs ...
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XR82C684 Field Note: The “shaded” options are only available in the 68 pin PLCC Table 15. Bit Rate Selection via the Clock Select Registers, CSR[3:0] and CSR[7:4] for Oscillator frequency of 3.6864 MHz Field Note: The “shaded” options are only ...
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Table 15 Table 15A Register Table 16. Command Register Controls Over the Extend Bit Note: If the user programs either nibble of the Clock Select Register (CSRn[7:4] or CSRn[3:0]) with values ranging from using ...
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XR82C684 Figure 33. Example of a Serial Data Transmission System Figure 34. Receiver (1X) Sampling, if the RX Clock is Slightly Faster Than the TX clock Figure 34 Figure 34 Figure 35 ...
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Received Data 0 Actual Data 0 Figure 35. Illustration of an Error Due to Receiver Drift Figure XR82C684 Figure ...
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XR82C684 Figure 36. The Typical Sampling Pattern of Each Receiver Within the XR82C684 Device D.6 Application Examples using the Timing Control Block Example A: Using the BRG Table 15 ...
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Table 14 Example B: Programming the Bit Rate via the Counter/Timer Please note that this particular bit rate is not offered by the BRG. In this case the user can do the following. Please note that when the QUART is ...
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XR82C684 D.7 Explanation of Clock Timing Signals Symbol tCLK - X1/CLK (External) High or Low Time fCLK - X1/CLK Crystal High or Low Time tCTC - Counter/Timer External Clock High or Low Time - IP2/IP10 Input Please ...
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E. INPUT PORT Input Port Alternate Function(s) Note: this input is Active Low, for the CTS func- tion. XR82C684 E.1 Alternate Functions for the Input Port Table 17 Approach to Program Alternate Functions Section D.3. Section D.3. ...
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XR82C684 Input Port Alternate Function(s) Note: This input is Active Low for the CTS func- tion. Note: “Shaded” Input Port pin and Alternate Functions are only available in the 68 Pin PLCC package. Table 17. Listing of Alternate Function for ...
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Bit 7 Bit 6 Bit 5 Table 19. Input Port Configuration Register 2 - IPCR2 Please note that the applicable bits, within each of the ACR registers, are shaded. Bit 7 Bit 6 Bit 5 Table 4 Table 20. ...
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XR82C684 Table 1 Table 1 F.1 Writing Data to the OPRs/Output Port Pins F.1.1 Set Output Port Bits Command For Example ...
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Figure 38. Illustration of the “Set Output Port Bit #1” Command And Its Effect on the Output Port Register and the State of the Output Port Pins Figure ...
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XR82C684 F.1.2 Clear Output Port Bits Command Figure 39. Illustration of the “Clear Output Port BIT #1” Command and Its Effect on the Output Port Register 1 and the State of the Output Port Pins 1 1 ...
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Figure 39A. Illustration of the “Clear Output Port Bit #2” Command and Its Effect on Output Port Register 2 and the State of the Output Port Pins F.2 Output Port Configuration Registers (OPCR1 and OPCR2) Table 22 ...
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XR82C684 Output Port TXCC_1X: TXCC_16X: RXCC_1X: TXCD_1X: RXCD_1X: C/T2_RDY: when used as the Counter/Timer Ready Output. RXRDY/-FFULL_C: Active-low output for the RXRDY/FFULL_C function. RXRDY/-FFULL_D: Active-low output for the RXRDY/FFULL_D function. -TXRDY_C: -TXRDY_D: Note: The “shaded” Output Port pin alternate functions ...
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F.3 44 Pin PLCC Packaged QUARTs G. SERIAL CHANNELS and D XR82C684 Section B.2 Section D G.1 Transmitter (TSR and THR) Figure 40 ...
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XR82C684 Figure 40. A Simplified Drawing Depicting the Transmit Shift Register and the Transmit Holding Register Figure 41. The Output Waveform of the Transmitter While Sending 5D (8-N-1 Protocol) Figure 41 ...
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Section B.2 G.2 Receiver (RSR and RHR) Figure 42. A Simplified Drawing of the Receiver Shift Register and Receiver Holding Register XR82C684 Please note that if a 16X clock is selected for the receiver, this over-sampling procedure occurs with each ...
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XR82C684 Receiver Errors Bit 7 Bit 6 Rx RTS Rx Interrupt Error Mode Control Select Table 25. Mode Registers - MR1A, MR1B, MR1C, MR1D G.3 Mode Registers, MR1n and MR2n Bit 5 Bit 4 Bit 3 Parity Mode Select Bit ...
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Bit 7 Bit 6 Bit 5 Channel Mode Tx RTS Control Table 26. Mode Registers - MR2A, MR2B, MR2C, MR2D MR1n[7] - Receiver Request to Send Control Figure 42 MR1n[6] - Receiver Interrupt Select MR1n[5] - Error Mode Select Bit ...
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XR82C684 Figure 42 Figure 43. A Block Diagram Depicting Normal Mode Operation Figure 44 ...
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Figure 44. A Block Diagram Depict Automatic Echo Mode Local Loopback Mode Figure 45 XR82C684 ...
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XR82C684 Figure 45. A Block Diagram Depicting Local Loopback Mode Operation ...
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Remote Loopback Mode Figure 46 Note: The CPU has no access ot the Serial Data during Remote Loopback Mode. Figure 46. A Block Diagram Depicting Remote Loopback Mode MR2n[5] - Transmitter Request-to-Send Control Figure 49 XR82C684 MR2n[4] - Clear to ...
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XR82C684 G.4 Status Register, SRn Bit 7 Bit 6 Bit 5 Received Framing Parity Error Break Error Table 27. Status Register - SRA, SRB, SRC, SRD SRn[7] Received Break Table 2 Bit 4 Bit 3 Bit 2 Overrun TXEMT TXRDY ...
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Table 2 SRn[4] Overrun Error SRn[3] Transmitter Empty (TXEMT) SRn[2] Transmitter Ready (TXRDY) SRn[1] FIFO Full (FFULL) XR82C684 SRn[0] Receiver Ready (RXRDY Special Modes Of Operation H.1 RTS/CTS Handshaking H.1.1 Receiver-Controlled RTS/CTS Handshaking Figure ...
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XR82C684 Figure 47. Block Diagram and Timing Sequence of two QUARTs connected in the Figure 47 Section G.3 Section G.3 Receiver-RTS Controlled Configuration ...
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Figure 47 Figure 48. A Flow Diagram Depicting An Algorithm That Could Be Used to Apply The Receiver-controlled RTS/CTS Handshaking Mode XR82C684 Figure 48 ...
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XR82C684 H.1.2 Transmitter-Controlled RTS/CTS Handshaking Figure 49. Block Diagram and Timing Sequence of Two QUARTs Connected in the Figure 49 Section G.3 Transmitter-RTS Controlled Configuration ...
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Figure 50. A Flow Diagram depicting an Algorithm That Could Be Used to Realize the Transmitter-Controlled RTS/CTS Handshaking Mode XR82C684 Figure 50 ...
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XR82C684 H.2 Multi-drop (8051 9 bit) Mode. H.2.1 Concept of Multi-Drop Mode Figure 51 Figure 51. An Illustration Depicting the Concept of Multi-Drop Mode Figure 52. Bit Format of Character Data Being Transmitted in the Multi-Drop Mode Figure 52 H.2.2 ...
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Figure 53. A Flow Diagram Depicting a Procedure that Can Be Used to Transmit Characters in the Multi-Drop Mode Receiver Operation During Multi-Drop Mode XR82C684 ...
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XR82C684 Figure 54. A Flow Diagram Depicting a Procedure That Can Be Used to Receive Characters in the Multi-Drop Mode H.3 Standby Mode Figure 54 • ...
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I. COMMENTS ABOUT THE XR82C684 IN 44 PIN PLCC J. PROGRAMMING Bit 7 Bit 6 Rx RTS Con- Rx Int Select Error Mode trol Table 28. Mode Registers 1: MR1A, MR1B, MR1C, MR1D Bit 7 Bit 6 Bit ...
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XR82C684 Bit 7 Bit 6 Bit 5 Miscellaneous Commands Section B.2 Table 31. Command Registers: CRA, CRB, CRC, CRD Bit 7 Bit 6 Bit 5 Received Framing Parity Error Break Error Table 32. Status Registers: SRA, SRB, SRC, SRD Bit ...
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Bit 7 Bit 6 Bit 5 BRG Set Counter/Timer #2 Mode and Source Select Table 13 Table 36. Auxiliary Control Register 2: ACR2 Bit 7 Bit 6 Bit 5 Delta IP3 Delta IP2 Delta IP1 Table 37. Input Port Configuration ...
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XR82C684 Bit 7 Bit 6 Bit 5 Input Port Delta Break RXRDY/ Change D FFULLD Bit 7 Bit 6 Bit 5 Table 43. Counter/Timer Upper Byte Register, CTUR (applies to CTUR1 and CTUR2) Bit 7 Bit 6 Bit 5 Table ...
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Figure 56. Reset Timing Figure 57. XR82C684 Read and Write Cycle Timing (88 Mode) XR82C684 ...
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XR82C684 Figure 58. XR82C684 Z Mode Interrupt Cycle Timing (88 - Mode) ...
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Figure 59. XR82C684 Read Cycle Timing (68 - Mode) Figure 60. XR82C684 Write Cycle Timing (68 - Mode) XR82C684 ...
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XR82C684 Figure 61. XR82C684 Interrupt Cycle Timing (68 - Mode) Figure 62. Port Timing ...
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Figure 63. Interrupt Timing XR82C684 Figure 64. Clock Timing XR82C684 XR82C684 ...
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XR82C684 Figure 65. Transmitter Timing Figure 66. Receiver Timing ...
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LEAD PLASTIC LEADED CHIP CARRIER SYMBOL Note: The control dimension is the inch column (PLCC) Rev. 1. INCHES MILLIMETERS MIN MAX MIN ...
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XR82C684 68 LEAD PLASTIC LEADED CHIP CARRIER SYMBOL Note: The control dimension is the inch column (PLCC) Rev INCHES MILLIMETERS MIN MAX MIN MAX C 45 x ...
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XR82C684 ...