XR20M1172IG28-F Exar Corporation, XR20M1172IG28-F Datasheet - Page 57

• Manufacturer Part Number: XR20M1172IG28-F
• Description: IC UART FIFO I2C/SPI 64B 28TSSOP
• Manufacturer: Exar Corporation

Specifications of XR20M1172IG28-F

• Number Of Channels: 2, DUART
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 1.62 V ~ 3.63 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 16 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.62 V
• Supply Current: 250 uA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• No. Of Channels: 2
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 1.62V To 3.63V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: TSSOP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1298-5

REV. 1.0.1
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................. 27
5.0 ELECTRICAL CHARACTERISTICS ..................................................................................................... 43
PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9
PACKAGE DIMENSIONS (28 PIN TSSOP - 4.4
A
T
DC E
AC E
AC E
AC E
R
YPICAL
BSOLUTE
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY .................................................................................. 27
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................... 27
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ................................................................................ 27
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 29
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ........................................................................................ 30
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ........................................................................................ 32
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE . 33
4.8 LINE STATUS REGISTER (LSR) - READ ONLY.............................................................................................. 35
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................... 36
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 37
4.11 TRANSMISSION CONTROL REGISTER (TCR) - READ/WRITE (REQUIRES EFR BIT-4 = 1) .................... 37
4.12 TRIGGER LEVEL REGISTER (TLR) - READ/WRITE (REQUIRES EFR BIT-4 = 1) ...................................... 37
4.13 TRANSMIT FIFO LEVEL REGISTER (TXLVL) - READ-ONLY ...................................................................... 37
4.14 RECEIVE FIFO LEVEL REGISTER (RXLVL) - READ-ONLY......................................................................... 37
4.15 GPIO DIRECTION REGISTER (IODIR) - READ/WRITE ................................................................................. 38
4.16 GPIO STATE REGISTER (IOSTATE) = READ/WRITE .................................................................................. 38
4.17 GPIO INTERRUPT ENABLE REGISTER (IOINTENA) - READ/WRITE ......................................................... 38
4.18 GPIO CONTROL REGISTER (IOCONTROL) - READ/WRITE ....................................................................... 38
4.19 EXTRA FEATURES CONTROL REGISTER (EFCR) - READ/WRITE............................................................ 39
4.20 BAUD RATE GENERATOR REGISTERS (DLL, DLM AND DLD[3:0]) - READ/WRITE................................ 39
4.21 ENHANCED FEATURE REGISTER (EFR) ..................................................................................................... 40
EVISION
T
T
T
T
T
T
T
T
T
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
LECTRICAL
LECTRICAL
LECTRICAL
LECTRICAL
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 27
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION.................................................................. 28
4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 29
4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 29
4.21.1 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE .............................. 41
P
8: INTERNAL REGISTERS DESCRIPTION. S
9: I
10: T
11: P
12: R
13: R
14: S
15: S
16: UART RESET STATES .............................................................................................................................................. 42
20. C
21. SCL D
22. I2C-B
23. W
24. M
25. GPIO P
26. R
27. R
28. T
29. SPI-B
30. SPI W
31. SPI W
32. SPI W
33. R
34. R
35. R
H
ACKAGE
M
NTERRUPT
ISTORY
AXIMUM
RANSMIT AND
ARITY SELECTION
EGISTER AT
EGISTER AT
AMPLING
OFTWARE
RANSMIT
LOCK
ECEIVE
ECEIVE
EAD
EAD
EAD
ODEM
RITE
C
C
C
C
US
MSR
IOS
RHR
HARACTERISTICS
HARACTERISTICS
HARACTERISTICS
HARACTERISTICS
US
RITE
RITE
RITE
ELAY
T
T
T
..................................................................................................................................... 55
IN
I
O
IMING
NPUT
S
HERMAL
I
I
T
R
T
NTERRUPT
NTERRUPT
R
TATE TO
F
I
OURCE AND
O
I
IMING
ATE
NTERRUPT
IMING
NTERRUPT
MCR
MCR
THR
LOW
TO
TO
ATINGS
A
A
A
UTPUT
FTER
R
DDRESS
DDRESS
............................................................................................................................................................. 44
P
C
C
S
ECEIVE
IN
.......................................................................................................................................................... 49
C
TO
LEAR
LEAR
ELECT
D
TO
TO
........................................................................................................................................................ 33
ONTROL
I
...................................................................................................................................................... 46
C
IAGRAM
NTERRUPT
R
R
.................................................................................................................................................... 48
C
LEAR
C
DTR O
DTR O
ESET
.................................................................................................................... 43
.................................................................................................................................................. 47
ESISTANCE
C
LEAR
LEAR
RX INT .................................................................................................................................... 52
O
O
M
P
FIFO T
LEAR
............................................................................................................................................... 40
RIORITY
FFSET
FFSET
ODEM
GPIO INT .......................................................................................................................... 52
.......................................................................................................................................... 46
.......................................................................................................................................... 46
F
............................................................................................................. 43
......................................................................................................................................... 48
TX INT............................................................................................................................. 51
- UART C
- I2C-
- SPI-
UTPUT
UTPUT
UNCTIONS
....................................................................................................................................... 48
..................................................................................................................................... 47
RIGGER
INT ............................................................................................................................. 51
0
0
X
X
L
6 ............................................................................................................................. 34
7 ............................................................................................................................. 34
EVEL
BUS
S
S
BUS
D
WITCH
WITCH
ATA
L
........................................................................................................................ 40
....................................................................................................................... 30
EVEL
LOCK
T
T
IMING
IMING
................................................................................................................. 50
................................................................................................................. 50
(M
HADED BITS ARE ENABLED WHEN
S
ARGIN OF ERROR
ELECTION
.................................................................................... 44
S
S
II
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
PECIFICATIONS
PECIFICATIONS
mm
............................................................................................ 31
) ...................................................... 54
mm
: ± 15%).............................................. 43
).............................................. 53
........................................................ 45
........................................................ 49
EFR B
IT
-4=1 ......................................... 26
XR20M1172