ST16C2550IQ48-F Exar Corporation, ST16C2550IQ48-F Datasheet
ST16C2550IQ48-F
Specifications of ST16C2550IQ48-F
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ST16C2550IQ48-F Summary of contents
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JANUARY 2011 GENERAL DESCRIPTION The ST16C2550 (C2550 dual universal asynchronous receiver and transmitter (UART). The ST16C2550 is an improved version of the PC16550 UART with higher operating speed and faster access times. The C2550 provides enhanced functions with ...
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ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO IGURE IN UT SSIGNMENT RXB 4 RXA 5 ST16C2550 6 TXRDYB# 48-pin TQFP TXA 7 8 TXB OP2B# 9 CSA# 10 ...
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... EMPERATURE R ANGE 0°C to +70°C Active. See the ST16C2550CQ48 for new designs. 0°C to +70°C Active 0°C to +70°C Active -40°C to +85°C Active. See the ST16C2550IQ48 for new designs. -40°C to +85°C Active -40°C to +85°C Active 3 ST16C2550 D S EVICE ...
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ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO PIN DESCRIPTIONS Pin Description 40-PDIP 44-PLCC N AME DATA BUS INTERFACE ...
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REV. 4.4.1 Pin Description 40-PDIP 44-PLCC N AME TXRDYB RXRDYB MODEM OR SERIAL I/O INTERFACE TXA 11 13 RXA 10 11 RTSA CTSA DTRA ...
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ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO Pin Description 40-PDIP 44-PLCC N AME CTSB DTRB DSRB CDB RIB OP2B ANCILLARY SIGNALS ...
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REV. 4.4.1 1.0 PRODUCT DESCRIPTION The ST16C2550 (C2550) integrates the functions of two 16C550 Universal Asynchrounous Receiver and Transmitter (UART). Each UART is independently controlled having its own set of device configuration registers. The C2550 provides serial asynchronous receive data ...
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ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The C2550 data ...
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REV. 4.4.1 2.4 Channel A and B Internal Registers Each UART channel in the C2550 has a standard register set for controlling, monitoring and data loading and unloading. The configuration register set is compatible to those already available in the ...
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ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO 2.7 Crystal Oscillator or External Clock Input The C2550 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the device. The CPU data bus does ...
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REV. 4.4 obtain maximum data rate necessary to use full rail swing on the clock input. See external clock operating frequency over power supply voltage chart in F IGURE Requires a 2K ohms pull-up resistor on ...
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ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO The C2550 divides the basic external clock by 16. The basic 16X clock provides table rates to support standard and custom applications using the same system design. The Baud Rate Generator divides ...
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REV. 4.4 IGURE RANSMITTER Data Byte 16X Clock Transmit Shift Register (TSR) 2.9.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with bytes of transmit data. The THR empty flag ...
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ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO 2.10.1 Receive Holding Register (RHR) - Read-Only The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register. It provides the receive data interface ...
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REV. 4.4.1 2.11 Internal Loopback The C2550 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 11 shows ...
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ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO 3.0 UART INTERNAL REGISTERS Each of the UART channel in the C2550 has its own set of configuration registers selected by address lines A0, A1 and A2 with CSA# or CSB# selecting ...
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REV. 4.4 ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR Bit IER RD/ ...
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ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO 4.3.1 IER versus Receive FIFO Interrupt Mode Operation When the receive FIFO (FCR BIT and receive interrupts (IER BIT are enabled, the RHR interrupts (see ISR bits 2 ...
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REV. 4.4.1 4.4 Interrupt Status Register (ISR) - Read-Only The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on ...
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ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO 4.5 FIFO Control Register (FCR) - Write-Only This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and select the DMA mode. The DMA, and ...
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REV. 4.4.1 LCR[1:0]: TX and RX Word Length Select These two bits specify the word length to be transmitted or received. BIT LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified ...
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ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format. • LCR[5] = logic 0, parity is not forced (default). • LCR[5] = ...
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REV. 4.4.1 MCR[3]: OP2# Output / INT Output Enable This bit enables and disables the operation of INT, interrupt output. If INT output is not used, OP2# can be used as a general purpose output. • Logic 0 = INT ...
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ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO This bit is set to a logic 1 whenever the transmitter goes idle set to logic 0 whenever either the THR or TSR contains a data character. In the FIFO ...
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REV. 4.4.1 MSR[7]: CD Input Status Normally this bit is the compliment of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose ...
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ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (48-TQFP) Thermal Resistance (44-PLCC) Thermal Resistance (40-PDIP) ELECTRICAL CHARACTERISTICS DC ...
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REV. 4.4.1 AC ELECTRICAL CHARACTERISTICS TA (-40 + FOR INDUSTRIAL GRADE PACKAGE LOAD WHERE APPLICABLE P S ARAMETER YMBOL - Crystal Frequency CLK Clock Pulse Duration OSC External ...
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ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO AC ELECTRICAL CHARACTERISTICS TA (-40 + FOR INDUSTRIAL GRADE PACKAGE LOAD WHERE APPLICABLE P S ARAMETER YMBOL T Reset Pulse ...
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REV. 4.4 IGURE ODEM NPUT UTPUT IOW # Active RTS# Change of state DTR# CD# CTS# DSR# INT IOR# RI IGURE ATA US EAD IMING A0-A2 Valid Address ...
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ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO F 16 IGURE ATA US RITE IMING A0-A2 Valid Address T AS CSA#/ CSB# IOW# D0- & I IGURE ECEIVE EADY NTERRUPT RX Start ...
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REV. 4.4 & I IGURE RANSMIT EADY NTERRUPT TX Start D0:D7 (Unloading) Bit IER[1] ISR is read enabled INT* T WRI T SRT TXRDY IOW# (Loading data into THR) *INT is cleared when the ...
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ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO F 20 & I IGURE ECEIVE EADY NTERRUPT Start Stop Bit Bit RX D0:D7 D0: INT RX FIFO fills Trigger Level or RX Data Timeout ...
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REV. 4.4 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX D0:D7 S (Unloading) IER[1] ISR is read enabled INT* T WRI TXRDY# IOW# (Loading data into FIFO) *INT is cleared when the ...
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ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO PACKAGE DIMENSIONS (48 PIN TQFP - Seating Plane Note: The control dimension is the millimeter column SYMBOL ...
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REV. 4.4.1 PACKAGE DIMENSIONS (44 PIN PLCC Note: The control dimension is the millimeter column SYMBOL 2.97V TO ...
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ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO PACKAGE DIMENSIONS (40 PIN PDIP Seating Plane L B Note: The control dimension is the millimeter column SYMBOL ...
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... Corrected the "Voltage at any pin" to "GND-0.3V to +5.5V" in the "Absolute maximum ratings" table on the page 26. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...