M52277EVB Freescale Semiconductor, M52277EVB Datasheet - Page 23

• Manufacturer Part Number: M52277EVB
• Description: BOARD DEMO FOR MCF5227
• Manufacturer: Freescale Semiconductor
• Series: ColdFire®r
• Type: MCUr

Specifications of M52277EVB

• Contents: Board
• Silicon Manufacturer: Freescale
• Core Architecture: Coldfire
• Core Sub-architecture: Coldfire V2
• Silicon Core Number: MCF52
• Silicon Family Name: MCF5227x
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MCF52277
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.7.2
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports either standard
SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time.
5.7.2.1
The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the memory bus
clock, when operating in SDR mode on write cycles and relative to SD_DQS on read cycles. The device’s SDRAM controller
is a DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must still be supplied to the
device for each data beat of an SDR read. The processor accomplishes this by asserting a signal named SD_SDR_DQS during
read cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the
SD_SDR_DQS signal and its usage.
Freescale Semiconductor
Num
SD1 Clock Period
SD2 Pulse Width High
SD3 Pulse Width Low
SD4 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD6 SD_SDR_DQS Output Valid
SD7 SD_DQS[3:2] input setup relative to SD_CLK
Frequency of Operation
SD_CS[1:0] - Output Valid
SD_CS[1:0] - Output Hold
SDRAM Bus
SDR SDRAM AC Timing Specifications
FB_CSn, FB_BE/BWEn
Characteristic
MCF5227x ColdFire
FB_D[31:X]
FB_A[23:0]
FB_CLK
FB_R/W
FB_OE
FB_TS
FB_TA
Table 14. SDR Timing Specifications
Figure 10. Flexbus Write Timing
FB1
ADDR[31:X]
S0
®
FB2
Microprocessor Data Sheet, Rev. 8
FB6
ADDR[23:0]
S1
t
t
t
DQVSDCH
Symbol
SDCHACV
SDCHACI
t
t
t
t
SDCKH
SDCKH
DQSOV
SDCK
DATA
S2
SD_CLK
FB7
0.25 ×
12.0
0.45
0.45
Min
2.0
60
—
—
S3
0.40 × SD_CLK
FB3
0.5 × SD_CLK
Self timed
83.33
16.67
+ 1.0
Max
0.55
0.55
—
Electrical Characteristics
SD_CLK
SD_CLK
MHz
Unit
ns
ns
ns
ns
ns
Notes
1
2
3
3
4
5
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