EM250-RCM-R Ember, EM250-RCM-R Datasheet
EM250-RCM-R
Specifications of EM250-RCM-R
Related parts for EM250-RCM-R
EM250-RCM-R Summary of contents
Page 1
... EM250 Single-Chip ZigBee/802.15.4 Solution Integrated 2.4GHz, IEEE 802.15.4-compliant trans- ceiver: • Robust RX filtering allows co-existence with IEEE 802.11g and Bluetooth devices • - 99dBm RX sensitivity (1% PER, 20byte packet) • + 3dBm nominal output power • Increased radio performance mode (boost mode) gives - 100dBm sensitivity and + 5dBm transmit power • ...
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... Mode and Application Mode. The EmberZNet stack runs in System Mode with full access to all areas of the chip. Application code runs in Application Mode with limited access to the EM250 resources; this allows for the scheduling of events by the application developer while preventing modification of re- stricted areas of memory and registers ...
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... Integrated Voltage Regulator 6 Programming and Debug Interface (SIF Module) 7 Typical Application 8 Mechanical Details 9 QFN48 Footprint Recommendations 10 IR Temperature Profile 11 Part Marking 12 Ordering Information 13 Shipping Box Label 14 Register Address Table 15 Abbreviations and Acronyms 16 References 17 Revision History EM250 100 101 102 106 107 108 ...
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... Refer to Table 17 and Table 18 for selecting alternate pin functions. 120-0082-000S EM250 Figure 1. EM250 Pin Assignment Page 4 SIF_MOSI SIF_MISO SIF_CLK GPIO10, RXD, MI, MSCL, TMR1IB.2 GPIO9, TXD, MO, MSDA, TMR1IA.2 GPIO8, VREF_OUT, TMR1CLK, TMR2ENMSK, IRQA GPIO7, ADC3 GPIO6, ADC2, TMR2CLK,TMR1ENMSK VDD_PADS GPIO5, ADC1, PTI_DATA GPIO4, ADC0, PTI_EN GPIO3, nSSEL, TMR1IB.1 ...
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... Bias setting resistor Analog pad supply (1.8V); should be connected to VREG_OUT Logic-level control for external RX/TX switch The EM250 baseband controls TX_ACTIVE and drives it high (1.8V) when in TX mode. (Refer to Table 6 and section 4.2.2.) Analog pad supply (1.8V); should be connected to VREG_OUT Active low chip reset (internal pull-up) 32 ...
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... EM250 Pin # Signal Direction MOSI O MOSI I TMR1IA GPIO1 I/O MISO I MISO O SDA I/O TMR2IA VDD_PADS Power 24 GPIO2 I/O MSCLK O MSCLK I SCL I/O TMR2IB GPIO3 I/O nSSEL I TMR1IB GPIO4 I/O ADC0 Analog 120-0082-000S Description SPI master data out of Serial Controller SC2 Enable SC2-3M with ...
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... Digital I/O Enable GPIO10 with GPIO_CFG[7:4] UART receive data of Serial Controller SC1 Enable SC1-4A or SC1-2 with GPIO_CFG[7:4] Page 7 GPIO_CFG[9] GPIO_CFG[9] GPIO_CFG[11] GPIO_CFG[11] , select UART with SC1_MODE , select SPI with , enable master with SC1_MODE 2 C with SC1_MODE , select UART with SC1_MODE EM250 120-0082-000S ...
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... EM250 Pin # Signal Direction MI I MSCL I/O TMR1IB SIF_CLK I 35 SIF_MISO O 36 SIF_MOSI I 37 nSIF_LOAD I/O 38 GND Power 39 VDD_FLASH Power 40 GPIO16 I/O TMR1OB O TMR2IB.3 I IRQD I 41 GPIO15 I/O TMR1OA O TMR2IA.3 I IRQC I 42 GPIO14 I/O TMR2OB O TMR1IB.3 I IRQB I 43 GPIO13 I/O TMR2OA O TMR1IA ...
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... VREG_OUT 24MHz crystal oscillator or left open when using external clock input on OSCA 24MHz crystal oscillator or external clock input Ground supply pad in the bottom center of the package forms Pin 49 (See the EM250 Reference Design for PCB considerations.) Page 9 ...
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... The radio transmitter utilizes an efficient architecture in which the data stream directly modulates the VCO. An integrated PA boosts the output power. The calibration of the TX path as well as the output power is con- trolled by digital logic. If the EM250 used with an external PA, the TX_ACTIVE signal should be used to control the timing of the external switching logic. ...
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... Serial Controller SC1 can be configured for SPI (master-only), I Serial Controller SC2 can be configured for SPI (master or slave The EM250 has an ADC integrated which can sample analog signals from four GPIO pins single-ended or differ- entially. In addition, the unregulated voltage supply VDD_PADS, regulated supply VDD_PADSA, voltage refer- ence VREF, and GND can be sampled ...
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... SIF_MOSI, nSIF_LOAD, OSC32A, OSC32B, nRE- SET, VREG_OUT Voltage on TX_ACTIVE, BIAS_R, OSCA, OSCB Storage temperature 3.2 Recommended Operating Conditions Table 3 lists the rated operating conditions of the EM250. Parameter Regulator input voltage (VDD_PADS) Core input voltage (VDD_24MHZ, VDD_VCO, VDD_RF, VDD_IF, VDD_PADSA, VDD_FLASH, VDD_PRE, VDD_SYNTH, VDD_CORE) Temperature range 3 ...
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... DC Electrical Characteristics Table 5 lists the DC electrical characteristics of the EM250. Note: Current Measurements were collected using the EmberZNet software stack Version 3.0.1. Parameter Regulator input voltage (VDD_PADS) Power supply range (VDD_CORE) Deep Sleep Current Quiescent current, including internal RC oscillator Quiescent current, including 32.768kHz oscillator ...
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... EM250 Table 6 contains the digital I/O specifications for the EM250. The digital I/O power (named VDD_PADS) comes from three dedicated pins (Pins 17, 23, and 28). The voltage applied to these pins sets the I/O voltage. Parameter Voltage supply Input voltage for logic 0 Input voltage for logic 1 ...
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... Transmit Table 8 lists the key parameters of the integrated IEEE 802.15.4 transmitter on the EM250. Note: Transmit Measurements were collected with Ember’s EM250 Lattice Balun Reference Design (Version B1) at 2440MHz and using the EmberZNet software stack Version 3.0.1. The Typical number indicates one standard deviation below the mean, measured at room temperature (25° ...
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... Error vector magnitude Carrier frequency error Load impedance PSD mask relative PSD mask absolute 3.5.3 Synthesizer Table 9 lists the key parameters of the integrated synthesizer on the EM250. Parameter Test Conditions Frequency range Frequency resolution Lock time From off, with correct VCO DAC setting Relock time Channel change or RX/TX turnaround (IEEE 802 ...
Page 17
... RSSI and CCA The EM250 calculates the RSSI over an 8-symbol period as well as at the end of a received packet. It utilizes the RX gain settings and the output level of the ADC within its algorithm. The linear range of RSSI is specified to be 40dB over all temperatures. At room temperature, the linear range is approximately 60dB (-90 dBm to - 30dBm) ...
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... There is no damage to the EM250 from this problem. This issue will rarely oc- cur in the field as ZigBee Nodes will be spaced far enough apart. If nodes are close enough for it to occur in the field, the MAC and networking software treat the packet as not having been received and therefore the MAC level and network level retries resolve the problem without upper level application being notified ...
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... PHY TX and RX packets (in a non-intrusive manner) between the MAC and baseband modules asynchronous 500kbps interface and cannot be used to inject packets into the PHY/MAC interface. The two signals from the EM250 are the frame signal (PTI_EN) and the data signal (PTI_DATA). The PTI is supported by InSight Desktop. ...
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... EM250 4.6 Embedded Memory As shown in Figure 3, the program side of the address space contains mappings to both integrated Flash and RAM blocks. Physical Flash 0x1FFFF (16 kB Accessible only from Data Address Space) 0x1C000 0x1BFFF 112 kB Flash for Code 0x0000 120-0082-000S Program Address Space ...
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... Figure 4. Data Address Space 4.6.1 Flash Memory The EM250 integrates 128kB of Flash memory. The Flash cell has been qualified for a data retention time of >100 years at room temperature. Each Flash page size is 1024 bytes and is rated to have a guaranteed 1,000 write/erase cycles. The Flash memory has mappings to both the program and data side address spaces. On the program side, the first 112kB of the Flash memory are mapped to the corresponding first 56k word addresses to allow for code storage, as shown in Figure 3 ...
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... When the asynchronous external reset signal, nRESET (Pin 13), is driven low for a time greater than 200ns, the EM250 resets to its default state. An integrated glitch filter prevents noise from causing an inadvertent reset to occur. If the EM250 placed in a noisy environment, an external LC Filter or supervisory reset circuit is recommended to guarantee the integrity of the reset signal. ...
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... When nRESET asserts, all EM250 registers return to their reset state as defined by Table 42. In addition, the EM250 consumes 1.5mA (typical) of current when held in RESET. 4.9 Reset Detection The EM250 contains multiple reset sources. The reset event is logged into the reset source register, which lets the CPU determine the cause of the last reset ...
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... Current consumption 4.11.2 Low-Frequency Oscillator The optional low-frequency crystal source for the EM250 is a 32.768kHz crystal. Table 13 lists the require- ments for the low-frequency crystal. The low-frequency crystal may be used for applications that require greater accuracy than can be provided by the internal RC oscillator. When using the internal RC Oscillator, the pins OSC32A and OSC32B can be left open (or not connected) ...
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... Frequency variation with supply 4.12 Random Number Generator The EM250 allows for the generation of random numbers by exposing a randomly generated bit from the RX ADC. Analog noise current is passed through the RX path, sampled by the receive ADC, and stored in a regis- ter. The value contained in this register could be used to seed a software-generated random number. The Em- berZNet stack utilizes these random numbers to seed the Random MAC Backoff and Encryption Key Genera- tors ...
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... Activity on a serial interface may also be configured to wake the EM250, though actual reception of data is not re-enabled until the EM250 has finished waking up. Depending on the speed of the serial data possible to finish waking up in the middle of a byte. Care must be taken to reset the serial interface between bytes and discard any garbage data before the rest ...
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... GPIO, Serial Controllers (SC1 and SC2), General Purpose Timers, ADC, and Event Manager are enabled. 5.1 GPIO The EM250 has 17 multi-purpose GPIO pins that can be configured in a variety of ways. All pins have the fol- lowing programmable features: Selectable as input, output, or bi-directional. ...
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... EM250 The GPIO_DBG ing for alternate GPIO functions as listed in Table 17. Refer to Table 1 for individual pin alternate functions. Table 18 defines the alternate functions routed to the GPIO. To allow more flexibility, the timer signals can come from alternative sources (e.g., TIM1IA.1, TIM1IA.2, TIM1IA.3), depending on what serial controller func- tions are used ...
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... SC1-3M + SC2-4S + CAP2-2 + CAP1-2h mode+GPIO[12 TMR2OA TMR2OB TMR1OA TMR1OB Page 29 Enable GPIO4 Enable GPIO5 Enable GPIO6 Enable GPIO7 Enable GPIO8 mode+GPIO[12,11,10,9,3,2,1,0] mode+GPIO[12,11, 3, mode+GPIO[12, 3 mode+GPIO[12,11,10,9,3, mode+GPIO[ 3 mode+GPIO[12 3,2,1,0] mode+GPIO[12,11, 3 mode+GPIO[ 3,2,1,0] mode+GPIO[12 3, mode+GPIO[12,11,10,9,3 mode+GPIO[12,11, 3,2,1,0] mode+GPIO[ 3, Enable GPIO13 Enable GPIO14 Enable GPIO15 Enable GPIO16 EM250 120-0082-000S ...
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... EM250 Always GPIO Connected Input Pin Functions Timer Functions 0 IO TMR1IA.1 (when CAP1-0 mode TMR2IA.2 (when CAP2-1 mode TMR2IB.2 (when CAP2-1 mode TMR1IB.1 (when CAP1-0 mode TMR2CLK, TMR1ENMSK IRQA TMR1CLK, TMR2ENMSK 9 IO TMR1IA.2 (when CAP1-1 or CAP1-1h mode TMR1IB.2 (when CAP1-1 mode) ...
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... Write the output level of GPIO[15:0] pins. The value read may not match the actual value on the pin. Page 0-R 0 0-R 0-R 0-R 0-R 0-R 0 0-R 0-R 0 0-R 0-R 0 0-RW 0-RW 0-RW 0- EM250 0 GPIO_INH 0 0-R 0 0-R 0 GPIO_ OUTH 0- 0-RW 0-RW 0 120-0082-000S ...
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... EM250 GPIO_SETH [0x4708 0-R 0 0-R 0 GPIO_SETH [0] GPIO_SETL [0x470A 0-W 0-W 0-W 0 GPIO_SETL [15:0] GPIO_CLRH [0x470C 0-R 0 0-R 0 GPIO_CLRH [0] 120-0082-000S 13 12 0-R 0 0-R 0 Set the output level of GPIO[16] pin. Only writing ones into this register will have an effect. Any bit that has one written to it will cause the corresponding bit in ...
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... Any bit that has one written to it will cause the corresponding bit in become 0-R 0-R 0 0-R 0-R 0 Enable the output of GPIO[16] pin 0-RW 0-RW 0-RW GPIO_DIRL GPIO_DIRL 0-RW 0-RW 0- Enable the output of GPIO[15:0] pins. Page 0-W 0-W 0-W 0 0-R 0 0-R 0 0-RW 0-RW 0-RW 0- EM250 8 0-W 0 GPIO_OUTL 8 0-R 0 GPIO_ DIRH 0- 0-RW 0-RW 0 120-0082-000S ...
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... EM250 GPIO_DIRSETH [0x4718 0-R 0 0-R 0 GPIO_DIRSETH [0] GPIO_DIRSETL [0x471A 0-W 0-W 0-W 0-W 0-W 0 GPIO_DIRSETL [15:0] GPIO_DIRCLRH [0x471C 0-R 0 0-R 0 GPIO_DIRCLRH [0] 120-0082-000S 13 12 0-R 0 0-R 0 Set the output enable of GPIO[16] pin. Only writing ones into this register will have an effect. Any bit that has one written to it will cause the corresponding bit in become 1 ...
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... GPIO_PDL GPIO_PDL 0-RW 0-RW 0- Set this bit to enable pull-down resistors on GPIO[15:0] pins 0-R 0-R 0 0-R 0-R 0 Set this bit to enable pull-up resistors on GPIO[16] pin. Page 35 EM250 10 9 0-W 0-W 0-W 0-W 0-W 0 GPIO_DIRL 10 9 0-R 0-R 0 GPIO_PDH 0-R 0-R 0- 0-RW ...
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... EM250 GPIO_PUL [0x4726 0-RW 0-RW 0-RW 0- GPIO_PUL [15:0] GPIO_WAKEL [0x4728 0-RW 0-RW 0-RW 0- GPIO_WAKEL [15:0] GPIO_INTCFGA [0x4630 0-R 0 GPIO_INTMOD 0-RW 0- GPIO_INTFILT [8] GPIO_INTMOD [7:5] 120-0082-000S 0-RW 0-RW 0-RW GPIO_PUL GPIO_PUL 0-RW 0-RW 0- Set this bit to enable pull-up resistors on GPIO[15:0] pins 0-RW 0-RW ...
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... Set this bit to enable GPIO IRQD filter. GPIO IRQD input edge triggering selection disabled rising falling both edges active high triggered active low trigger; 6,7 = reserved. Page 37 EM250 0-R 0-R 0- GPIO_INTFILT 0-R 0-R 0 ...
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... EM250 INT_GPIOCFG [0x4628 0-R 0 0-R 0 INT_GPIOD [3] INT_GPIOC [2] INT_GPIOB [1] INT_GPIOA [0] INT_GPIOFLAG [0x4610 0-R 0 0-R 0 INT_GPIOD [3] INT_GPIOC [2] INT_GPIOB [1] INT_GPIOA [0] GPIO_DBG [0x4710 0-R 0 0-R 0 GPIO_DBG [1:0] 120-0082-000S 0-R 0-R 0 INT_GPIOD 0-R 0-R 0- GPIO IRQD interrupt enable. GPIO IRQC interrupt enable. GPIO IRQB interrupt enable. ...
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... Serial Controller SC1 The EM250 SC1 module provides asynchronous (UART) or synchronous (SPI block diagram of the SC1 module. CPU Interrupt SC1_MODE SC1 TX DMA channel SC1 RX DMA channel The full-duplex interface of the SC1 module can be configured into one of these three communication modes, but it cannot run them simultaneously ...
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... EM250 5.2.1 UART Mode The SC1 UART controller is enabled with The UART mode contains the following features: Baud rate (300bps up to 921kbps) Data bits ( Parity bits (none, odd, or even) Stop bits ( The following signals can be made available on GPIO pins: TXD RXD ...
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... When the DMA controller is transferring the data from in the register. The second scheme is to as- SC1_UARTCFG register. in the SC1_UARTRXOVF SC1_UARTSTAT Page 41 EM250 data regis- SC1_DATA in the SC1_UARTTXIDLE in the SC1_UARTTXFREE in the SC1_UARTTXFREE SC1_UARTPARERR register is set ...
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... EM250 receive overrun occur during DMA operation, the hardware generates the til the RX FIFO is drained. Once the DMA marks a RX error, there are two conditions that will clear the error indication: setting the appropriate priate DMA buffer after it has unloaded. Interrupts are generated on the following events: ...
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... TX[7] TX[6] TX[5] out MI RX[7] RX[6] RX[5] in Same as above except LSB first instead of MSB first Illegal Illegal in the register to get set also. SC1_SPISTAT Page 43 EM250 TX[4] TX[3] TX[2] TX[1] TX[0] RX[4] RX[3] RX[2] RX[1] RX[0] TX[4] TX[3] TX[2] TX[1] TX[0] RX[4] ...
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... EM250 ther reception is dropped and the register bit hardware generates the til the RX FIFO is drained. Once the DMA marks a RX error, there are two conditions that will clear the error indication: setting the appropriate priate DMA buffer after it has unloaded. Receiving a character always requires transmitting a character case when a long stream of receive char- acters is expected, a long sequence of (dummy) transmit characters must be generated ...
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... C Master controller supports generation of various frame segments controlled with the register bits , , SC_I2CSTART SC_I2CSTOP SC_I2CSEND rizes these frames. register. Table 22 shows the rate set- SC1_RATELIN 2 C (400kbps) operation Nominal Rate Programming SC1_RATELIN and in the SC_I2CRECV SC1_I2CCTRL1 Page 45 EM250 SC1_RATEEXP registers. Table 23 summa- 120-0082-000S ...
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... EM250 SC1_I2CCTRL1 SC1-2 mode SC1-2 mode SC1-2 mode SC1-2 mode SC1-2 mode - SC1-4M mode SC1-4A mode 120-0082-000S 2 Table 23. SC1 I C Master Frame Segments Frame Segments start segment SCL outSLAVE SCL out SDA out SDA outSLAVE SCL outSLAVE SCL out SDA TX[7] ...
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... SC1_I2CSTAT in the SC_I2CRECV data register. Alternatively, the register bit SC1_DATA SC_I2CRXNAK 2 C slave device. ) completed ( transition of Page 47 EM250 2 C segments. All nec receive frame segment is YES 2 C master or in the SC_I2CSTOP data register, followed by setting register, waiting ...
Page 48
... EM250 Character transmitted ( transition of Character received ( transition of Received and lost character while receive FIFO was full (Receive overrun error) Transmitted character while transmit FIFO was empty (Transmit underrun error) To generate interrupts to the CPU, the interrupt masks in the abled. 5.2.4 Registers SC1_MODE [0x44AA] ...
Page 49
... SC1_UARTODD SC1_UARTPAR 0-RW 0- bit in this register has no effect when this bit is set. register should be configured for mode SC1-4A for hardware handshake with Page 49 EM250 0-R 0-R 0 SC1_UARTFRAC 0-R 0-R 0- 0-R 0 SC1_UART2STP SC1_UART8BIT SC1_UARTRTS 0-RW 0- 120-0082-000S ...
Page 50
... EM250 SC1_UARTSTAT [0x44A4 0-R 0 SC1_ 0 UARTTXIDLE UARTPARERR 0-R 1 SC1_UARTTXIDLE [6] SC1_UARTPARERR [5] SC1_UARTFRMERR [4] SC1_UARTRXOVF [3] SC1_UARTTXFREE [2] SC1_UARTRXVAL [1] SC1_UARTCTS [0] SC1_RATELIN [0x44B0 0-R 0 0-R 0 SC1_RATELIN [3:0] 120-0082-000S 0-R 0-R 0 SC1_ SC1_ SC1_ UARTFRMERR UARTRXOVF 0-R 0-R 0 This bit is set when the transmit FIFO is empty and the transmitter is idle. ...
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... Clock polarity configuration is selected with clearing this bit for a rising leading edge and setting this bit for a falling leading edge. Page 0-R 0 SC1_RATEEXP 0-RW 0- 0-R 0 SC_SPIORD SC_SPIPHA 0-RW 0- EM250 8 0 0-R 0 SC_SPIPOL 0-RW 0 120-0082-000S ...
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... EM250 SC1_SPISTAT [0x44A0 0-R 0 0-R 0 SC_SPITXIDLE [3] SC_SPITXFREE [2] SC_SPIRXVAL [1] SC_SPIRXOVF [0] SC1_I2CCTRL1 [0x44A6 0-R 0 0-R 0 SC_I2CSTOP [3] SC_I2CSTART [2] SC_I2CSEND [1] SC_I2CRECV [0] SC1_I2CCTRL2 [0x44A8 0-R 0 0-R 0 SC_I2CACK [0] 120-0082-000S 0-R 0-R 0 SC_SPITXIDLE 0-R 0-R 0 This bit is set when the transmit FIFO is empty and the transmitter is idle. This bit is set when the transmit FIFO is ready to accept at least one byte. ...
Page 53
... Reading this bit as one indicates DMA processing for buffer A is active or pending. Reading this bit as zero indicates DMA processing for buffer A is complete or idle. Page 0-R 0 SC_I2CRXFIN SC_I2CTXFIN 0-R 0 0-R 0-R 0 SC_TXLODA SC_RXLODB 0-RW 0- EM250 8 0-R 0 SC_I2CRXNAK 0 0-R 0 SC_RXLODA 0-RW 0 120-0082-000S ...
Page 54
... EM250 SC1_DMASTAT [0x4496 0-R 0 SC1_RXPARB SC1_RXPARA SC_RXOVFB 0-R 0 SC1_RXFRMB [9] SC1_RXFRMA [8] SC1_RXPARB [7] SC1_RXPARA [6] SC_RXOVFB [5] SC_RXOVFA [4] SC_TXACTB [3] SC_TXACTA [2] SC_RXACTB [1] SC_RXACTA [0] SC1_RXCNTA [0x4490 0-R 0 0-R 0 SC1_RXCNTA [12:0] 120-0082-000S 13 12 0-R 0-R 0 SC_RXOVFA SC_TXACTB 0-R 0-R 0 This bit is set when DMA receive buffer B was passed a frame error from the lower hardware FIFO ...
Page 55
... DMA Start address (byte aligned) for receive buffer 1-R 0-RW 0-RW 1 SC1_RXENDA 0-RW 0-RW 0- DMA End address (byte aligned) for receive buffer A. Page 0-R 0-R SC1_RXCNTB 0-R 0 0-R 0-R SC1_TXCNT 0-R 0 0-RW 0-RW SC1_RXBEGA 0-RW 0- 0-RW 0-RW SC1_RXENDA 0-RW 0- EM250 8 0-R 0 0-R 0 0-RW 0- 0-RW 0-RW 0 120-0082-000S ...
Page 56
... EM250 SC1_RXBEGB [0x4484 0-R 1 0-RW 0- SC1_RXBEGB [12:0] SC1_RXENDB [0x4486 0-R 1 0-RW 0- SC1_RXENDB [12:0] SC1_TXBEGA [0x4488 0-R 1 0-RW 0- SC1_TXBEGA [12:0] SC1_TXENDA [0x448A 0-R 1 0-RW 0- SC1_TXENDA [12:0] 120-0082-000S 13 12 1-R 0-RW 0-RW 1 SC1_RXBEGB 0-RW 0-RW 0- DMA Start address (byte aligned) for receive buffer B. ...
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... DMA. The next error will only be recorded if the buffer unloads and is reloaded or the receive DMA is reset. Page 0-RW 0-RW SC1_TXBEGB 0-RW 0- 0-RW 0-RW SC1_TXENDB 0-RW 0- 0-R 0-R SC1_RXERRA 0-R 0 0-R 0-R SC1_RXERRB 0-R 0 EM250 8 0-RW 0- 0-RW 0- 0-R 0 0-R 0-R 0 120-0082-000S ...
Page 58
... EM250 INT_SC1CFG [0x4624 0-R 0-RW 0 INT_ SC1PARERR SC1FRMERR INT_ INT_SCTXFIN INT_SCRXFIN SCCMDFIN 0-RW 0- INT_SC1PARERR [14] INT_SC1FRMERR [13] INT_SCTXULDB [12] INT_SCTXULDA [11] INT_SCRXULDB [10] INT_SCRXULDA [9] INT_SCNAK [8] INT_SCCMDFIN [7] INT_SCTXFIN [6] INT_SCRXFIN [5] INT_SCTXUND [4] INT_SCRXOVF [3] INT_SCTXIDLE [2] INT_SCTXFREE [1] INT_SCRXVAL [0] 120-0082-000S 13 12 0-RW 0-RW 0-RW INT_ INT_ INT_ SCTXULDB SCTXULDA INT_ INT_SCRXOVF SCTXUND ...
Page 59
... Transmit buffer underrun interrupt pending. Receive buffer overrun interrupt pending. Transmitter idle interrupt pending. Transmit buffer free interrupt pending. Receive buffer has data interrupt pending. Page 0-RW 0-RW INT_ INT_ SCRXULDB SCRXULDA INT_ INT_ SCTXIDLE SCTXFREE 0-RW 0- EM250 8 0-RW INT_SCNAK INT_SCRXVAL 0-RW 0 120-0082-000S ...
Page 60
... EM250 5.3 Serial Controller SC2 The EM250 SC2 module provides synchronous (SPI or I the SC2 module. CPU Interrupt SC2_MODE SC2 TX DMA channel SC2 RX DMA channel The full-duplex interface of the SC2 module can be configured into one of these two communication modes, but it cannot run them simultaneously. To reduce the interrupt service requirements of the CPU, the SC2 module contains buffered data management schemes ...
Page 61
... SC_SPIMST SC2_SPICFG EXP ) SC2_RATELIN ) (see Table 24). The register bits SC_SPIORD register. SC2_SPICFG to SC_SPIPOL=1 SC_SPIPOL=0 0xFE Page 61 EM250 register. register. Since the range for both ), clock SC_SPIPOL , SC_SPIPOL without subsequently setting ) to be transmitted immediately 120-0082-000S ...
Page 62
... EM250 SC2_SPICFG Serialized SC2 SPI transmit data is driven to the output pin MOSI. SC2 SPI master data is received from the in- put pin MISO. To generate slave select signals to SPI slave devices, other GPIO pins have to be used and their assertion must be controlled by software. ...
Page 63
... INT_SC2FLAG SC_SPITXFREE SC_SPIRXVAL SC_TXACTA/B ) SC_RXACTA/B INT_SC2CFG cleared in the SC_SPIMST ) (see Table 25). The register bits SC_SPIORD registers. SC2_SPICFG to SC_SPIPOL=1 SC_SPIPOL=0 0xFE Page 63 EM250 register, or loading the appro- ), which is determined 0xFF SC_SPITXIDLE ) SC_SPITXIDLE ) ) ) and register must be en- INT_CFG register. SC2_SPICFG ), clock phase SC_SPIPOL , ...
Page 64
... EM250 SC2_SPICFG When the slave select (nSSEL) signal is asserted (by the Master), SC2 SPI transmit data is driven to the output pin MISO and SC2 SPI data is received from the input pin MOSI. When the slave select (nSSEL) signal is deas- serted (by the Master), no data is transferred on the MISO or MOSI pins and the output pin MISO is tri-stated. ...
Page 65
... SPI master begins clocking data, then the first byte of data is transmitted without a byte of padding. Because of this race condition and the inability of the SPI master to know the current, internal state of the EM250 best to design a protocol around SPI slave interaction that handles this race condition and avoids potential issues. Some possible protocol solutions are: SPI slave does not place data into the transmit FIFO until the SPI status indicates that the SPI master has begun clocking data ...
Page 66
... EM250 Transmitted character while transmit FIFO was empty (Transmit underrun error) To generate interrupts to the CPU, the interrupt masks in the abled. 2 5.3 Master Mode 2 The SC2 I C controller is only available in master mode. The SC2 The I C Master controller supports Standard (100kbps) and Fast (400kbps) I not implemented, so multiple master applications are not supported ...
Page 67
... I C stop segment - after frame with NACK or stop SCL outSLAVE SCL out SDA out SDA outSLAVE No pending frame segment Illegal Illegal Illegal Page 67 EM250 re-start segment - after transmit or frame with NACK SCL outSLAVE SCL out SDA out SDA outSLAVE transmit segment ...
Page 68
... EM250 (Re)start and stop segments are initiated by setting the register bits SC2_I2CCTRL1 SC_I2CCMDFIN For initiating a transmit segment, the data has to be written to the ting the register bit ternatively, the register bit A receive segment is initiated by setting the register bit until it clears, and then reading from the ...
Page 69
... NOTE: Changing the register is only allowed when the serial controller is SC2_RATEEXP disabled, when is 0. SC2_MODE The exponential component (EXP) of the clock rate as seen in the equation: rate = 24MHz / ( 2 * (LIN + 1) * (2^EXP) ) Page 69 EM250 0-R 0-R 0 SC2_RATELIN 0-RW 0-RW 0- 0-R 0-R ...
Page 70
... EM250 SC2_SPICFG [0x442C 0-R 0 SC_SPIRXDRV 0-R 0 SC_SPIRXDRV [5] SC_SPIMST [4] SC_SPIRPT [3] SC_SPIORD [2] SC_SPIPHA [1] SC_SPIPOL [0] SC2_SPISTAT [0x4420 0-R 0 0-R 0 SC_SPITXIDLE [3] SC_SPITXFREE [2] SC_SPIRXVAL [1] SC_SPIRXOVF [0] 120-0082-000S 0-R 0-R 0 SC_SPIMST SC_SPIRPT 0-RW 0-RW 0- NOTE: Changing the register is only allowed when the serial controller is SC2_SPICFG disabled, when is 0. ...
Page 71
... This bit is set when a START or STOP command completes. It autoclears on next bus activ- ity. This bit is set when a byte is received. It autoclears on next bus activity. This bit is set when a byte is transmitted. It autoclears on next bus activity. This bit is set when a NACK is received from the slave. It autoclears on next bus activity. Page 71 EM250 10 9 0-R 0-R 0 ...
Page 72
... EM250 SC2_DMACTRL [0x4418 0-R 0 SC_TXDMARST 0-R 0 SC_TXDMARST [5] SC_RXDMARST [4] SC_TXLODB [3] SC_TXLODA [2] SC_RXLODB [1] SC_RXLODA [0] 120-0082-000S 0-R 0-R 0 SC_RXDMARST SC_TXLODB 0-W 0-W 0- Setting this bit will reset the transmit DMA. The bit is autocleared. Setting this bit will reset the receive DMA. This bit is autocleared. ...
Page 73
... A byte offset (from 0) which points to the location in DMA receive buffer A where the next byte will be written. When the buffer fills and subsequently unloads, this register wraps around and holds the value zero (pointing back to the first location in the buffer). Page 73 EM250 10 9 0-R ...
Page 74
... EM250 SC2_RXCNTB [0x4412 0-R 0 0-R 0 SC2_RXCNTB [12:0] SC2_TXCNT [0x4414 0-R 0 0-R 0 SC2_TXCNT [12:0] SC2_RXBEGA [0x4400 0-R 1 0-RW 0- SC2_RXBEGA [12:0] SC2_RXENDA [0x4402 0-R 1 0-RW 0- SC2_RXENDA [12:0] 120-0082-000S 0-R 0-R 0-R 0 SC2_RXCNTB 0-R 0-R 0 byte offset (from 0) which points to the location in DMA receive buffer B where the next byte will be written ...
Page 75
... SC2_TXBEGA 0-RW 0-RW 0- DMA Start address (byte aligned) for transmit buffer 1-R 0-RW 0-RW 1 SC2_TXENDA 0-RW 0-RW 0- DMA End address (byte aligned) for transmit buffer A. Page 75 EM250 10 9 0-RW 0-RW SC2_RXBEGB 0-RW 0- 0-RW 0-RW SC2_RXENDB 0-RW 0- 0-RW 0-RW SC2_TXBEGA 0-RW 0-RW ...
Page 76
... EM250 SC2_TXBEGB [0x440C 0-R 1 0-RW 0- SC2_TXBEGB [12:0] SC2_TXENDB [0x440E 0-R 1 0-RW 0- SC2_TXENDB [12:0] SC2_RXERRA [0x441A 0-R 0 0-R 0 SC2_RXERRA [12:0] SC2_RXERRB [0x441C 0-R 0 0-R 0 SC2_RXERRB [12:0] 120-0082-000S 1-R 0-RW 0-RW 1 SC2_TXBEGB 0-RW 0-RW 0- DMA Start address (byte aligned) for transmit buffer B. 13 ...
Page 77
... Receive operation complete (I C) interrupt enable. Transmit buffer underrun interrupt enable. Receive buffer overrun interrupt enable. Transmitter idle interrupt enable. Transmit buffer free interrupt enable. Receive buffer has data interrupt enable. Page 77 EM250 10 9 0-RW 0-RW 0-RW INT_ INT_ INT_SCNAK SCRXULDB ...
Page 78
... INT_SCTXFREE [1] INT_SCRXVAL [0] 5.4 General Purpose Timers The EM250 integrates two general-purpose, 16-bit timers—TMR1 and TMR2. Each of the two timers contains the following features: Configurable clock source Counter load Two output compare registers Two input capture registers Can be configured to do PWM ...
Page 79
... CPU Interrupt isCapB TMR1_CAPB isCapA TMR1_CAPA TMR1_CNT 0 Edge- Pre- Counter detect Scaler AND TMR1_CFG Figure 9. Timer TMR1 Block Diagram Page 79 EM250 INT_EN INT_CFG[13] INT_FLAG[13] INT_TMRCFG INT_TMRFLAG TMR1_CMPCFGB Output Generation Output Generation Counter Comparison TMR1_CMPCFGA TMR1_TOP TMR1_CMPB TMR1_CMPA zero 120-0082-000S TMR1OB TMR1OA ...
Page 80
... EM250 TMR_CLK[1: TMR_PSCL[3: 0.. 11..15 TMR_EDGE 0 1 Note: All configuration changes do not take effect until the next edge of the timer's clock source. These functions are separately controlled for TMR1 and TMR2 by setting the bits , and TMR_EDGE 5.4.2 Timer Functionality (Counting) Each timer supports three counting modes: increasing, decreasing, or alternating (where the counting will in- crease, then decrease, then increase) ...
Page 81
... BIDIR: 0 (OFF), DOWN 0 (UP), 1SHOT: 1 (ON) EN 0xFFFF TOP CNT CMPB CMPA 0x0000 0 < starting CNT = threshold TOP INT_WRAP INT_CMPTOP INT_CMPB INT_CMPA INT_CMPZ BIDIR: 0 (OFF), DOWN 0 (UP), 1SHOT: 1 (ON) EN 0xFFFF TOP CNT CMPB CMPA 0x0000 0 < starting CNT > threshold TOP INT_WRAP INT_CMPTOP INT_CMPB INT_CMPA INT_CMPZ EM250 120-0082-000S ...
Page 82
... EM250 120-0082-000S BIDIR: 0 (OFF), DOWN 1 (DOWN), 1SHOT: 0 (OFF) EN 0xFFFF TOP CNT CMPB CMPA 0x0000 0 = starting CNT < threshold TOP INT_WRAP INT_CMPTOP INT_CMPB INT_CMPA INT_CMPZ BIDIR: 0 (OFF), DOWN 1 (DOWN), 1SHOT: 0 (OFF) EN 0xFFFF TOP CNT CMPB CMPA 0x0000 0 < starting CNT < threshold TOP INT_WRAP ...
Page 83
... BIDIR: 1 (ON), DOWN 0 (UP), 1SHOT: 1 (ON) EN 0xFFFF TOP CNT CMPB CMPA 0x0000 0 < starting CNT = threshold TOP INT_WRAP INT_CMPTOP INT_CMPB INT_CMPA INT_CMPZ BIDIR: 1 (ON), DOWN 0 (UP), 1SHOT: 1 (ON) EN 0xFFFF TOP CNT CMPB CMPA 0x0000 0 < starting CNT > threshold TOP INT_WRAP INT_CMPTOP INT_CMPB INT_CMPA INT_CMPZ EM250 120-0082-000S ...
Page 84
... EM250 120-0082-000S BIDIR: 1 (ON), DOWN 1 (DOWN), 1SHOT: 0 (ON) EN 0xFFFF TOP CNT CMPB CMPA 0x0000 0 = starting CNT < threshold TOP INT_WRAP INT_CMPTOP INT_CMPB INT_CMPA INT_CMPZ BIDIR: 1 (ON), DOWN 1 (DOWN), 1SHOT: 0 (ON) EN 0xFFFF TOP CNT CMPB CMPA 0x0000 0 < starting CNT < threshold TOP INT_WRAP ...
Page 85
... The output signals TMR1OA and TMR1OB from Timer 1, and TMR2OA and TMR2OB from Timer 2, are available on GPIO. For selecting alternate pin functions, refer to Table 17 and Table 18. Figure 14 and Figure 15 show examples of all timer output generation modes. or register. TMR1_TOP TMR2_TOP or register. TMR1_CMPA TMR2_CMPA or register. TMR1_CMPB TMR2_CMPB , , , and TMR1_CMPCFGB TMR2_CMPCFGA Page 85 EM250 or inverted TMR_CMPMOD registers. TMR2_CMPCFGB 120-0082-000S ...
Page 86
... EM250 Figure 14. Timer Output Generation Mode Example—Saw Tooth, Non-inverting 120-0082-000S Page 86 ...
Page 87
... TMR1_CAPCFGB TMR2_CAPCFGA Table 32. GPIO/Timer Trigger Conditioning TMR_CAPMOD[1:0] Detection mode 0 Disabled 1 Rising Edge 2 Falling Edge 3 Either Edge All glitch filters consist of a flip-flop-driven, 4-bit shift register clocked with the main 12MHz clock. TMR_CAPMOD[1:0] , and registers. TMR2_CAPCFGB Page 87 EM250 , and in the TMR_CAPFILT 120-0082-000S ...
Page 88
... EM250 5.4.5 Timer Interrupt Sources Each timer supports a number of interrupts sources: On overflow during up-count from all 1s to zero. On counter reaching output compare values stored in the TMR2_CMPB On counter reaching zero, On capturing events from GPIO. To generate interrupts to the CPU, the interrupt masks in the abled ...
Page 89
... Timer 1 threshold value 0-R 0-R 0 TMR_CMPINV 0-R 0-RW 0- Set this bit to enable output A. Set this bit to invert output A. Output mode selection bits. Refer to Table 31 for the modes. Page 89 EM250 0-RW 0-RW 0-RW 0-RW 0-RW 0- 1-RW 1-RW 1-RW 1-RW 1-RW 1- ...
Page 90
... EM250 TMR1_CMPCFGB [0x4510 0-R 0-R TMR_CMPEN 0-R 0 TMR_CMPEN [15] TMR_CMPINV [4] TMR_CMPMOD [3:0] TMR1_CMPA [0x4508 0-R 0-R TMR_CMPEN 0-R 0 TMR1_CMPA [15:0] TMR1_CMPB [0x450A 0-RW 0-RW 0-RW 0- TMR1_CMPB [15:0] TMR1_CAPCFGA [0x4512 0-R 0 TMR_CAPMOD 0-R 0- TMR_CAPFILT [8] TMR_CAPMOD [6:5] 120-0082-000S 0-R 0-R 0 TMR_CMPINV 0-R 0-RW 0-RW ...
Page 91
... Input edge triggering selection disabled rising falling both edges 0-R 0-R 0-R TMR1_CAPA TMR1_CAPA 0-R 0-R 0 Timer 1 capture A value 0-R 0-R 0-R TMR1_CAPB TMR1_CAPB 0-R 0-R 0 Timer 1 capture B value. Page 91 EM250 0-R 0-R 0- TMR_CAPFILT 0-R 0-R 0 0-R 0-R 0-R 0-R 0-R 0 ...
Page 92
... EM250 TMR2_CFG [0x458C 0-R 0 TMR_PSCL 0-RW 0- TMR_EXTEN [12] TMR_EN [11] TMR_BIDIR [10] TMR_DOWN [9] TMR_1SHOT [8] TMR_PSCL [7:4] TMR_FILT [3] TMR_EDGE [2] TMR_CLK [1:0] TMR2_CNT [0x4580 0-RW 0-RW 0-RW 0- TMR2_CNT [15:0] TMR2_TOP [0x4586 1-RW 1-RW 1-RW 1- TMR2_TOP [15:0] 120-0082-000S 0-R 0-RW 0-RW 0 TMR_EXTEN TMR_EN TMR_FILT 0-RW 0-RW 0-RW ...
Page 93
... TMR_CMPINV 0-R 0-RW 0- Set this bit to enable output B. Set this bit to invert output B. Output mode selection bits. Refer to Table 31 for the modes 0-RW 0-RW 0-RW TMR2_CMPA TMR2_CMPA 0-RW 0-RW 0- Timer 2 compare A value. Page 93 EM250 0-R 0-R 0 TMR_CMPMOD 0-RW 0-RW 0- 0-R 0-R 0 ...
Page 94
... EM250 TMR2_CMPB [0x458A 0-RW 0-RW 0-RW 0- TMR2_CMPB [15:0] TMR2_CAPCFGA [0x4592 0-R 0 TMR_CAPMOD 0-R 0- TMR_CAPFILT [8] TMR_CAPMOD [6:5] TMR2_CAPCFGB [0x4594 0-R 0 TMR_CAPMOD 0-R 0- TMR_CAPFILT [8] TMR_CAPMOD [6:5] TMR2_CAPA [0x4582 0-R 0-R 0-R 0 TMR2_CAPA [15:0] 120-0082-000S 0-RW 0-RW 0-RW TMR2_CMPB TMR2_CMPB 0-RW 0-RW 0- Timer 2 compare B value. ...
Page 95
... Timer 2 compare A interrupt enable. Timer 2 overflow interrupt enable. Timer 1 capture B interrupt enable. Timer 1 capture A interrupt enable. Timer 1 compare Top interrupt enable. Timer 1 compare Zero interrupt enable. Timer 1 compare B interrupt enable. Timer 1 compare A interrupt enable. Timer 1 overflow interrupt enable. Page 95 EM250 10 9 0-R 0-R 0-R 0 ...
Page 96
... EM250 INT_TMRFLAG [0x4614 0-R 0-RW 0 INT_ TMR2CAPB TMR2CAPA 0 INT_ TMR1CAPB TMR1CAPA 0-R 0- INT_TMR2CAPB [14] INT_TMR2CAPA [13] INT_TMR2CMPTOP [12] INT_TMR2CMPZ [11] INT_TMR2CMPB [10] INT_TMR2CMPA [9] INT_TMR2WRAP [8] INT_TMR1CAPB [6] INT_TMR1CAPA [5] INT_TMR1CMPTOP [4] INT_TMR1CMPZ [3] INT_TMR1CMPB [2] INT_TMR1CMPA [1] INT_TMR1WRAP [0] 120-0082-000S 13 12 0-RW 0-RW 0-RW INT_ INT_ INT_ TMR2CMPTOP TMR2CMPZ INT_ INT_ INT_ TMR1CMPTOP TMR1CMPZ ...
Page 97
... EM250 6 7 2048 4096 240 120 140 72 0.6 1.2 0.2 0.4 0.12 0.1 0.03 0.03 12.5 12 -69 -69 -94 -93 12.5 12.3 13.1 13.1 11.3 11.1 13 ...
Page 98
... EM250 The conversion rate is programmed by setting the the ADC can be chosen from various sources and is configured with the As described in Table 34, the ADC inputs can be single-ended (routed individually to ADC0, ADC1, ADC2, or ADC3) or differential (routed to pairs ADC0-ADC1 and ADC2-ADC3). For selecting alternate pin functions, refer to Table 17 and Table 18 ...
Page 99
... VDD. Corrected Sample ( ) = − VSS ( ) − << VSS − VREF VSS ( ) − << VSS × − VDD VSS Table 36. ADC Specifications Min. 1. VREF Page 99 EM250 Absolute Voltage × VREF ) = × VDD ) = Typ. Max. Unit 1.2 1. VREF V VREF V + VREF V VREF Ohm 120-0082-000S ...
Page 100
... EM250 5.5.1 Registers ADC_CFG [0x4902 0-R 0- 0-R 0 ADC_RATE [14:12] ADC_SEL [11:8] ADC_DITH [1] ADC_EN [0] ADC_DATA [0x4900 0-R 0-R 0-R 0 ADC_DATA [15:0] 120-0082-000S 13 12 0-RW 0-RW 0-RW ADC_RATE 0 0 0-R 0 ADC conversion rate selection. Refer to Table 33 for details. ADC input selection. Refer to Table 34 for details. ...
Page 101
... Event Manager The XAP2b core supports one IRQ and one wake-up input; however, the EM250 contains an advanced Event Manager that takes IRQ and WAKE_UP signals from a variety of internal and external sources and provides them to the XAP2b. The Event Manager allows for each event to be separately masked and cleared by the CPU, and ensures that all events are serviced properly and promptly ...
Page 102
... They have full access to second-level INT_periphCFG from application interference. Applications can also trigger a software interrupt by writing into the responsible for processing and acknowledging this interrupt. The EM250 also provides a global can be used to easily protect brief critical sections in application or system software. 5.6.1 Registers INT_EN [0x4618] ...
Page 103
... Sleep Timer interrupt enable. Write is ignored in Application Mode. Baseband interrupt enable. Write is ignored in Application Mode. SIF interrupt enable. Write is ignored in Application Mode. Software interrupt enable. Write is ignored in Application Mode. Page 103 0-RW 0-RW INT_MACRX INT_MACTX INT_SIF INT_SW 0-RW 0- EM250 8 0-RW INT_MACTMR 0 0-R 0 120-0082-000S ...
Page 104
... EM250 INT_FLAG [0x4600 0-RW 0-RW INT_WDOG INT_FAULT INT_SEC INT_SC2 0-R 0 INT_WDOG [15] INT_FAULT [14] INT_TMR [13] INT_GPIO [12] INT_ADC [11] INT_MACRX [10] INT_MACTX [9] INT_MACTMR [8] INT_SEC [7] INT_SC2 [6] INT_SC1 [5] INT_SLEEP [4] INT_BB [3] INT_SIF [2] INT_SW [1] 120-0082-000S 13 12 0-R 0-R 0-RW INT_TMR INT_GPIO INT_ADC INT_SC1 INT_SLEEP INT_BB 0-R 0-R 0 Watchdog low watermark interrupt pending. Write is ignored in Application Mode. ...
Page 105
... INT_SWCTRL INT_SWCTRL 0-RW 0-RW 0- Writing to this register generates software interrupt. Possible values to be written are explained and controlled in the EmberZNet software stack. Page 105 0-RW 0-RW INT_MACRX INT_MACTX INT_SIF INT_SW 0-RW 0- 0-RW 0-RW 0-RW 0- EM250 8 0-RW INT_MACTMR 0 0 0-RW 0-RW 0 120-0082-000S ...
Page 106
... Integrated Voltage Regulator The EM250 integrates a low dropout regulator to provide an accurate core voltage at a low quiescent current. Table 38 lists the specifications for the integrated voltage regulator. With the regulator enabled, the pads supply voltage VDD_PADS is stepped down to the 1.8V regulator output VREG_OUT. The VREG_OUT signal must be externally decoupled and routed to the 1 ...
Page 107
... SIF is a synchronous serial interface developed by Cambridge Consultants Ltd the primary programming and debug interface of the EM250. The SIF module allows external devices to read and write memory-mapped registers in real-time without changing the functionality or timing of the XAP2b core. See PCB Design with an EM250 (120-5026-000) for the PCB-level design details regarding the implementation of the SIF interface ...
Page 108
... VDD nets. For a complete reference design, please download one of the Ember Reference Designs from the Ember website (www.ember.com). The Balun provides the impedance transformation from the antenna to the EM250 for both TX and RX modes. Ember has developed reference designs based upon two balun topologies, a monolithic (ceramic) balun and a LC Lattice Balun ...
Page 109
... Table 39 contains a typical Bill of Materials for both the Ceramic and Lattice Balun Application circuits shown in Figure 16. The information within this table should be used for a rough cost analysis. It does not contain the decoupling capacitors. For a more detailed BOM, please refer to one of Ember’s EM250-based reference de- signs at support.ember.com. ...
Page 110
... EM250 8 Mechanical Details The EM250 package is a plastic 48-pin QFN that is 7mm x 7mm x 0.9mm. Figure 17 and Figure 18 illustrate the package dimensions for the EM250s. Please see Chapter 11 for more information about how to determine the assembly site. Top View Edge View Nx Detail B Figure 17 ...
Page 111
... Figure 17 illustrates the dimensions of EM250s assembled in either Wales (“W”) or China (“C”), while Figure 18 demonstrates the dimensions of EM250s assembled in Malaysia (“M”). As described within Ember document 121-1012-000_EM250 Supplier PCN.pdf, all dimensions except package height, A, and the pin lead length, L, are the same. Despite the differences, the recommended PCB footprint is the same for both package designs. ...
Page 112
... Figure 19 demonstrates the IPC-7351 recommended PCB Footprint for the EM250 (QFN50P700X700X90-49N). A ground pad in the bottom center of the package forms array of non-thermal vias should connect the EM250 decal center shown in Figure 19 to the PCB ground plane through the ground pad. In order to properly solder the EM250 to the footprint, the Paste Mask layer should have array of circular openings at 1 ...
Page 113
... IR Temperature Profile Figure 22 details the recommended solder reflow temperature profile for the EM250. The same profile should be used for both first and second reflows. Table 40 reflects the reflow parameters. Parameter Average Ramp Up Rate (from Tsoakmax to Tpeak) Minimum Soak Temperature (Tsoakmin) ...
Page 114
... EM250 11 Part Marking Figure 23 shows the part marking for the EM250. The circle in the top corner indicates pin 1. Pins are num- bered counter-clockwise from Pin 1 with 12 pins per package edge. where: ZZZZZZ.ZZ defines the production lot code. YYWW defines the year and week assembled. ...
Page 115
... EM250-RTR Reel, RoHS – contains 2000 units/reel EM250-RTB Tube, RoHS – contains 70 units/tube EM250-RTR Reel conforms to EIA specification 481. Table 41 describes the general tape and reel dimensions, while Figure 24 describes the tape, pocket, and sprocket dimensions in more detail. To order parts, contact Ember at +1-617-951-0200, or send your inquiry by email to sales@ember.com. Details about our international distributors can be found on our Web site: www ...
Page 116
... EM250 Figure 25 illustrates the tube dimensions. 120-0082-000S Figure 25. Tube dimension (in inches) Page 116 ...
Page 117
... Shipping Box Label Ember includes the following information on each tape and reel box label (EM250-RTR): Package Device Type Quantity (Bar coded) Box ID (Bar coded) Lot Number (Bar coded) Date Code (Bar coded) Figure 26 depicts the label position on the box. As shown in this figure, there can two date codes in a single tape and reel ...
Page 118
... EM250 14 Register Address Table Table 42 provides the address, reset value, and description of the registers in the EM250. These registers are accessible by the application (user). Block: SERIAL Address Name 4400 SC2_RXBEGA 4402 SC2_RXENDA 4404 SC2_RXBEGB 4406 SC2_RXENDB 4408 SC2_TXBEGA 440A SC2_TXENDA 440C SC2_TXBEGB ...
Page 119
... Timer 1 capture A R 0000 Timer 1 capture B RW FFFF Timer 1 threshold RW 0000 Timer 1 compare A RW 0000 Timer 1 compare B RW 0000 Timer 1 config RW 0000 Timer 1 output A config RW 0000 Timer 1 output B config RW 0000 Timer 1 input capture A config RW 0000 Timer 1 input capture B config Page 119 EM250 120-0082-000S ...
Page 120
... EM250 Block: TIMER2 Address Name 4580 TMR2_CNT 4582 TMR2_CAPA 4584 TMR2_CAPB 4586 TMR2_TOP 4588 TMR2_CMPA 458A TMR2_CMPB 458C TMR2_CFG 458E TMR2_CMPCFGA 4590 TMR2_CMPCFGB 4592 TMR2_CAPCFGA 4594 TMR2_CAPCFGB Block: EVENT Address Name 4600 INT_FLAG 4602 INT_MISS 460C INT_SC1FLAG 460E INT_SC2FLAG 4610 INT_GPIOFLAG ...
Page 121
... GPIO pin pull-down enable–lower bits RW 0000 GPIO pin pull-up enable–upper bits RW 0000 GPIO pin pull-up enable–lower bits RW 0000 GPIO wakeup monitor register 4900-4902 ADC control and status Type Reset R 0000 ADC data RW 0000 ADC config Page 121 EM250 120-0082-000S ...
Page 122
... EM250 15 Abbreviations and Acronyms Acronym/Abbreviation ACR AES AGC CBC-MAC CCA CCM CCM* CSMA CTR EEPROM ESD ESR FFD FIA GPIO IDE IF IP3 ISR kB kbps LF LNA LQI MAC MSL Msps O-QPSK PA PER PHY PLL POR PSD 120-0082-000S Meaning Adjacent Channel Rejection Advanced Encryption Standard Automatic gain control Cipher Block Chaining— ...
Page 123
... Packet Trace Interface PWM Pulse Width Modulation RoHS Restriction of Hazardous Substances RSSI Receive Signal Strength Indicator SFD Start Frame Delimiter SIF Serial Interface SPI Serial Peripheral Interface UART Universal Asynchronous Receiver/Transmitter VCO Voltage Controlled Oscillator VDD Voltage Supply Page 123 EM250 120-0082-000S ...
Page 124
... IEEE 802.15.4-2003 (http://standards.ieee.org/getieee802/download/802.15.4-2003.pdf) 2. IEEE 802.11g (http://standards.ieee.org/getieee802/download/802.11g-2003.pdf) 3. Bluetooth Core Specification v2.1 (http://bluetooth.com/Specification%20Documents/Core_V21__EDR.zip) 4. ZigBee Specification v1.1 (www.zigbee.org; ZigBee Document 053474) (ZigBee Alliance membership re- quired) 5. ZigBee Security Services Specification v1.0 (Document Number 03322r13) 6. Ember EM250 Reference Design (http://ember.com/products_documentation.html)) 120-0082-000S Page 124 ...
Page 125
... N Table 1. Pin Descriptions Table 2. Absolute Maximum Ratings Table 7. Receive Characteristics Section 5.1, GPIO Section 5.2.4, Registers Figure 19. PCB Footprint for the EM250 Chapter 9, Part Marking Chapter 10, Ordering Information Description of Change Corrected dimensions. Added specifications for Malaysia manufacture. Clarified the circumstances under which the registers can be changed. ...
Page 126
... EM250 Copyright © 2005–2010 Ember Corporation. All rights reserved. The information in this document is subject to change without notice. This document is believed to be accu- rate and reliable, but the statements contained herein are presented without expressed or implied warranty. EmberNet, EmberZNet, EmberZNet PRO, and Ember are trademarks of Ember Corporation. All other trade- marks are the property of their respective holders ...