ATA5743P6-TGQY Atmel, ATA5743P6-TGQY Datasheet - Page 20

IC RCVR ASK/FSK 600KHZ 20SOIC

ATA5743P6-TGQY

Manufacturer Part Number
ATA5743P6-TGQY
Description
IC RCVR ASK/FSK 600KHZ 20SOIC
Manufacturer
Atmel
Datasheet

Specifications of ATA5743P6-TGQY

Frequency
300MHz ~ 450MHz
Sensitivity
-110dBm
Data Rate - Maximum
10 kBaud
Modulation Or Protocol
ASK, FSK
Applications
RKE, Telemetering, Security Technology
Current - Receiving
7.5mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 105°C
Package / Case
20-SOIC (0.300", 7.50mm Width)
Operating Frequency (max)
450000kHz
Operating Temperature (min)
-40C
Operating Temperature (max)
105C
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Memory Size
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATA5743P6-TGQY
Manufacturer:
ATMEL
Quantity:
222
Part Number:
ATA5743P6-TGQY
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Figure 6-14. Timing Diagram of the Data Clock
Figure 6-15. Data Clock Disappears Because of a Timing Error
20
ATA5743
Dem_out
Data_out (DATA)
DATA_CLK
Dem_out
Data_out (DATA)
DATA_CLK
The limits for 2T are calculated as follows:
Lower limit of 2T: Lim_min_2T = (Lim_min + Lim_max) - (Lim_max - Lim_min)/2
Upper limit of 2T: Lim_max_2T = (Lim_min + Lim_max) + (Lim_max - Lim_min)/2
Note:
The data clock is available after the data clock control logic has detected the distance 2T (Start
bit), and then issues pulses with a delay of t
If the data clock control logic detects a timing or logical error (Manchester code violation), as
illustrated in
receiver remains in receiving mode and starts with the bit check. If the bit check was successful
and the start bit has been detected, the data clock control logic starts again with the generation
of the data clock (see
It is recommended to use the function of the data clock only in conjunction with the bit check 3, 6
or 9. If the bit check is set to 0 or the receiver is set to receiving mode via the pin POLLING/_ON,
the data clock is available if the data clock control logic has detected the distance 2T (Start bit).
Note that for Bi-phase-coded signals, the data clock is issued at the end of the bit.
If the result for “Lim_min_2T” or “Lim_max_2T” is not an integer value, it will be rounded up.
1
1
Receiving mode,
data clock control
logic active
Bit check ok
Bit-check mode
Timing error
Figure 6-15
1
1
Figure 6-17 on page
1
1
T
(
T
ee
and
ee
Preburst
< T
1
1
Lim_min
Figure 6-16 on page
T
OR T
1
1
2T
Lim_max
Start bit
Data
0
0
21).
Delay
< T
Receiving mode,
bit check active
ee
data clock control logic active
1
1
after the edges on pin DATA (see
< T
Receiving mode,
21, it stops the output of the data clock. The
Lim_min_2T
1
1
t
Delay
Data
OR T
0
0
ee
> T
1
1
Lim_max_2T
t
P_Data_Clk
0
0
)
4839B–RKE–08/05
Figure
6-14).

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