ATA5743P6-TGQY Atmel, ATA5743P6-TGQY Datasheet - Page 24

• Manufacturer Part Number: ATA5743P6-TGQY
• Description: IC RCVR ASK/FSK 600KHZ 20SOIC
• Manufacturer: Atmel

Specifications of ATA5743P6-TGQY

• Frequency: 300MHz ~ 450MHz
• Sensitivity: -110dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, Telemetering, Security Technology
• Current - Receiving: 7.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Operating Frequency (max): 450000kHz
• Operating Temperature (min): -40C
• Operating Temperature (max): 105C
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Figure 6-23. Controlled Noise Suppression
6.6
24
Configuration of the Receiver
Serial bi-directional
data line
(DATA_CLK)
POLLING/_ON
ATA5743
Bit-check
mode
Bit check ok
The ATA5743 receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT.
The registers can be programmed by means of the bi-directional DATA port. If the register con-
tents have changed due to a voltage drop, this condition is indicated by a certain output pattern
called reset marker (RM). The receiver must be reprogrammed in that case. After a power-on
reset (POR), the registers are set to default mode. If the receiver is operated in default mode,
there is no need to program the registers.
ters. As seen in
command (see section
register address. It selects the appropriate register to be programmed. To get a high program-
ming reliability, bit 15 (Stop bit), at the end of the programming operation, must be set to “0”.
Table 6-1.
Table 6-2.
Preburst
Bit 1
1
0
0
Bit 15
0
1
Data
Receiving mode
Effect of Bit 1 and Bit 2 on Programming the Registers
Effect of Bit 15 on Programming the Register
Bit 2
Table
1
0
x
Digital Noise
6-1, bit 1 defines if the receiver is set back to polling mode via the OFF
“Receiving Mode” on page
Action
The receiver is set back to polling mode (OFF command)
The OPMODE register is programmed
The LIMIT register is programmed
Action
The values will be written into the register (OPMODE or LIMIT)
The values will not be written into the register
OFF command
Start-up
mode
Table 6-3 on page 25
Bit-check
mode
Bit check ok
Preburst
16) or if it is programmed. Bit 2 represents the
Receiving mode
Data
shows the structure of the regis-
Digital Noise
Sleep
mode
4839B–RKE–08/05