ATA5724P3-TKQY Atmel, ATA5724P3-TKQY Datasheet - Page 12

• Manufacturer Part Number: ATA5724P3-TKQY
• Description: IC RCVR ASK/FSK UHF 20-SSOP
• Manufacturer: Atmel

Specifications of ATA5724P3-TKQY

• Frequency: 433MHz
• Sensitivity: -113dBm
• Data Rate - Maximum: 10 kbps
• Modulation Or Protocol: ASK, FSK
• Applications: General Purpose
• Current - Receiving: 11mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SOIC (0.200", 5.30mm Width)
• Operating Temperature (min): -40C
• Operating Temperature (max): 105C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 4.4mm
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Figure 8-1.
12
ATA5723/ATA5724/ATA5728
Polling Mode Flow Chart
NO
Sleep Mode:
All circuits for signal processing are
disabled. Only XTO and Polling logic are
enabled.
Output level on Pin IC_ACTIVE = > low
I
T
Start-up Mode:
The signal processing circuits are
enabled. After the start-up time (T
all circuits are in stable
condition and ready to receive.
Output level on Pin IC_ACTIVE = > high
I
T
Bit-check Mode:
The incoming data stream is
analyzed. If the timing indicates a valid
transmitter signal, the receiver is set to
receiving mode. Otherwise it is set to
Sleep mode.
Output level on Pin IC_ACTIVE = > high
I
T
Receiving Mode:
The receiver is turned on permanently
and passes the data stream to the
connected microcontroller.
It can be set to Sleep mode through an
OFF command via Pin DATA or
Polling/_ON.
Output level on Pin IC_ACTIVE = > high
I
S
S
S
S
Sleep
Startup
Bit-check
= I
= I
= I
= I
Soff
Son
Son
Son
= Sleep
OFF Command
Bit Check
X
OK ?
Sleep
YES
1024
T
Startup
Clk
)
Sleep:
X
T
T
T
Sleep
Clk
Startup
Bit-check
:
:
:
:
5-bit word defined by Sleep 0 to
Sleep 4 in OPMODE register
Extension factor defined by
XSleepStd according to Table 11-8
Basic clock cycle defined by f
and Pin MODE
Is defined by the selected baud rate
range and TClk. The baud-rate range
is defined by Baud 0 and Baud 1 in
the OPMODE register.
Depends on the result of the bit check
If the bit check is ok, T
depends on the number of bits to be
checked (N
data rate used.
If the bit check fails, the average
time period for that check depends
on the selected baud-rate range and
on T
defined by Baud 0 and Baud 1 in the
OPMODE register.
Clk
. The baud-rate range is
Bit-check
) and on the
Bit-check
XTO
9106E–RKE–07/08