TDA5230 Infineon Technologies, TDA5230 Datasheet - Page 102

• Manufacturer Part Number: TDA5230
• Description: IC RECEIVER ASK/FSK 28-TSSOP
• Manufacturer: Infineon Technologies
• Type: Receiverr

Specifications of TDA5230

• Package / Case: 28-TSSOP
• Frequency: 433MHz ~ 450MHz, 865MHz ~ 868MHz
• Sensitivity: -111dBm
• Data Rate - Maximum: 20 kbps
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, TPM, Security Systems
• Current - Receiving: 8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 3 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Operating Frequency: 870 MHz
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: SP000076520; TDA5230; TDA5230INTR

2.4.13
The Frame Synchronization Unit (Framer) synchronizes to a specific pattern to identify
the exact start of a data frame. This pattern is called TSI (Telegram Start Identifier).
There are different TSI modes selectable via the configuration:
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All SFR configuring the Frame Synchronization Generation Unit are supporting the dual
configuration capability (Config A and B). The Framer starts working in Slave Mode after
Symbol Sync found and in Self Polling Mode after wake up found and searches for a
frame until TSI is found or synchronization is lost. The input of the Framer is a sequence
of manchester coded data (Chips). Basically the Framer consists of two identical
correlators of 16 chips in length. It allows a Telegram Start Identifier (TSI) to be
composed of Manchester coded “Zeros” and “Ones”. The active length of each of the 16
chips correlators is defined independently in the TSILENA and TSILENB registers. The
pattern to match is defined as sequence of chips in the TSIPTA0, TSIPTA1, TSIPTB0
and TSIPTB1 registers.
Note that the RUNIN length shown in the figures below is the maximum needed RUNIN
with the length of 8 chips set in the register. The needed RUNIN time of the receiver can
be shorter by 1-2 chips. It depends on the expected data rate error, duty cycle error, and
the starting chip sequence of the protocol.
Data Sheet
TSI Mode 16-Bit, supporting a TSI length up to 16 bits or 32 chips
TSI Mode 8-Bit, supporting two independent TSI pattern of up to 8 bits length
TSI GAP Mode 8-Bit, supporting the TSI GAP mode
TSI Mode 8-Bit extended, identical to TSI Mode 8-Bit, but identifies which pattern
matches by adding a single bit to the data frame
Frame Synchronization
98
Functional Description
Version 4.0, 2007-06-01
TDA523x