TDA5230 Infineon Technologies, TDA5230 Datasheet - Page 121

• Manufacturer Part Number: TDA5230
• Description: IC RECEIVER ASK/FSK 28-TSSOP
• Manufacturer: Infineon Technologies
• Type: Receiverr

Specifications of TDA5230

• Package / Case: 28-TSSOP
• Frequency: 433MHz ~ 450MHz, 865MHz ~ 868MHz
• Sensitivity: -111dBm
• Data Rate - Maximum: 20 kbps
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, TPM, Security Systems
• Current - Receiving: 8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 3 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Operating Frequency: 870 MHz
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: SP000076520; TDA5230; TDA5230INTR

Known Problem on using FIFO Lock in combination with EOM Interrupt in Run
Mode Slave:
Indifferent to the described behavior in Run Mode Slave, the NINT sticks low for low
active Interrupt or high for high active interrupt, after an EOM Interrupt, if FIFO Lock is
enabled. NINT is reset after reading the FIFO. See also
Generation
FIFO Status Word
The FIFO Status Word is mixed to FIFO SPI transmission, and shows if there was an
overflow, and how many valid data bits are transmitted. The number of valid FIFO bits is
indicated at bit positions S0 to S5. S6 of the Status Word is always undefined.
Figure 62
If the Write Address Pointer outruns the Read Address Pointer, an overflow is indicated
in the FIFO Overflow Status bit in the FIFO Read Status Word at position S7. All 32 FIFO
bits and the bits S5 to S0 of the Status Word are undefined while the Overflow Status bit
is set.
If a TSI is detected after an overflow, the FIFO Overflow Status bit is cleared and the
entire data FIFO is initialized.
Initialization
Additionally there are two possibilities to initialize the Data FIFO.
•
•
Data Sheet
SDO
SDI
If the INITFIFO bit is set in the CMC0 register(“Init FIFO at Cycle Start”) the entire
Data FIFO is always initialized
If the FSINITFIFO-bit in CMC1 register is set, the entire Data FIFO is initialized when
a TSI is detected and the Data FIFO is not locked (“Init FIFO at Frame Start”).
a.) after switching to Run Mode Slave or
b.) switching from Self Polling Mode to Run Mode Self Polling.
high impedance Z
Unit.
SPI Data FIFO Read
I7
I6
I1
I0
D0
D1
32 FIFO Bits
117
D30
D31
S7
S6
Status Word
Chapter 2.4.17 Interrupt
Functional Description
Version 4.0, 2007-06-01
S1
S0
TDA523x