TDA5230 Infineon Technologies, TDA5230 Datasheet - Page 122

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TDA5230

Manufacturer Part Number
TDA5230
Description
IC RECEIVER ASK/FSK 28-TSSOP
Manufacturer
Infineon Technologies
Type
Receiverr
Datasheet

Specifications of TDA5230

Package / Case
28-TSSOP
Frequency
433MHz ~ 450MHz, 865MHz ~ 868MHz
Sensitivity
-111dBm
Data Rate - Maximum
20 kbps
Modulation Or Protocol
ASK, FSK
Applications
RKE, TPM, Security Systems
Current - Receiving
8mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Voltage - Supply
3 V ~ 3.6 V, 4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 105°C
Operating Frequency
870 MHz
Operating Supply Voltage
3.3 V, 5 V
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
SP000076520
TDA5230
TDA5230INTR

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CMC0:
ADDR:
CMC1:
ADDR:
2.4.16
In addition to the FIFO functionality, the TDA5230 offers the received data in a
Transparent Mode. In this mode, the Manchester decoded data is available at an
external pin.
This is the same data that is written into the FIFO. This means that data is only available
after a frame synchronization. Wake up pattern, RUNIN and TSI are not visible. If the
FIFO is locked, no data will be written in the Tranparent Mode.
Two pins can be configured to act as the RX data output (CLKOUT/RXD or alternatively
RX-RUN/RXD). The pin NINT/NSTR acts as a data strobe signal. The strobe signal is
active high and has a delay of TBIT/16 relative to the data bit and a duration of TBIT/16.
Configuration of the Transparent Mode is done in the CMC1 register.
Data Sheet
Bit R/W Description
Bit R/W Description
7
4
3
W
W
W
0x02
0x03
Chip Mode Control Register 0
Chip Mode Control Register 1
Transparent Mode
INITFIFO: Init FIFO at Cycle Start
This Initialization of the FIFO can be configured in both Slave Mode and Self
Polling Mode. In Slave Mode, this occurs at the beginning of the Slave Run
Mode. In Self Polling Mode, the initialization is done after Wake up found
(switching from Self Polling Mode to Run Mode Self Polling).
0: No Init
1: Init FIFO
FIFOLK: Lock Data FIFO at EOM
0: FIFO lock is disabled
1: FIFO lock is enabled at EOM (see also Chapter FIFO)
FSINITFIFO: Init FIFO at Frame Start
0: No Init
1: Init
118
Functional Description
Reset Value: 0x40
Reset Value: 0x00
Version 4.0, 2007-06-01
TDA523x

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