TDA5230 Infineon Technologies, TDA5230 Datasheet - Page 20

• Manufacturer Part Number: TDA5230
• Description: IC RECEIVER ASK/FSK 28-TSSOP
• Manufacturer: Infineon Technologies
• Type: Receiverr

Specifications of TDA5230

• Package / Case: 28-TSSOP
• Frequency: 433MHz ~ 450MHz, 865MHz ~ 868MHz
• Sensitivity: -111dBm
• Data Rate - Maximum: 20 kbps
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, TPM, Security Systems
• Current - Receiving: 8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 3 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Operating Frequency: 870 MHz
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: SP000076520; TDA5230; TDA5230INTR

2.3
Figure 8
2.4
The RF frontend of the chip contains an LNA followed by an Image Reject Mixer that
converts the incoming RF-signal down to IF with adjustable gain from RFIN to IF-OUT.
Channel selection is achieved by up to two external ceramic IF filters, which narrow the
channel bandwidth. The multistage amplifier performs the limitation of the IF signal and
generation of the RSSI signal. The limited IF signal at its output drives the input of the
digital FSK Demodulator. The gain and offset of the generated RSSI signal can be
digitally adjusted. An A/D converter acts as an interface from the analog RSSI signal
path to the Digital Receiver.
The Digital Receiver performs data filtering, offset cancellation and Manchester
decoding of the received signals after they are demodulated. The chip also offers a
Data Sheet
VDDD1V5
GNDRF
VDD5V
GNDD
GNDA
RFIN+
VDDA
VDDD
RFIN-
P-ON
LNA
VCO
Functional Block Diagram
3.3V → 1.5V
Functional Block Description
5V → 3.3V
Regulator
Regulator
Voltage-
Voltage-
XTAL1
Functional Block Diagram
IR-Mixer
I
Divider
Loop-
Filter
I/Q-
IF-OUT
Crystal-Oscillator
Q
Low-Power
Trimming
Ceramic-Filter
Charge-
Pump
Power-Up
10.7 MHz
Reset
PLL-Divider
5V → 3.3V
Regulator
Detector
Voltage-
Phase-
XTAL2
Brownout-
Detector
Driver-
Amp.
f
IF-
sys
Reference-
Divider
CLKOUT/RXD
Ceramic-Filter
Generation-
10.7 MHz
Transparent-Mode Unit
Clock-
Unit
f
CLKOUT
LIM-IN+
NINT/NSTR
LIM-IN-
16
RSSI-Generation
RX-RUN/RXD
IF-Limiter
Master Control Unit
Polling-Timer Unit
Scanner
ID
ID-
Detector
Wakeup
WU
Chip-Data
RSSI
Sync
FSync
EOM
Data
FIFO
Functional Description
NCS
A
ASK
Version 4.0, 2007-06-01
SPI-Interface
D
SCK
Code-Violation Detector
Data-Clock Recovery &
RSSI-Peak-Detectors &
Matched Data-Filter &
Manchester-Decoder
DIGITAL-RECEIVER
Offset-Cancellation
Signal-MUX
Data-Slicer
SFR
Digital FSK-Demodulator
Framer &
SDI
SDO
TDA523x
Number
Serial-
FSK