TDA5251 Infineon Technologies, TDA5251 Datasheet
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TDA5251 Summary of contents
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... heet, Versio n 1.1, 2 007-02-26 TDA5251 ...
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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... heet, Versio n 1.1, 2 007-02-26 TDA5251 ...
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... Controller Area Network (CAN): License of Robert Bosch GmbH 2007-02-26 V1 2003-02-18 ® , ARCOFI -BA, ARCOFI ® ® ® 56, FALC -E1, FALC ® ® -S, ISAC -S TE, ISAC ® ® , SICOFI , SICOFI TDA5251 F1 ® ® ® -SP, DigiTape , EPIC ® ® -LH, IDEC , IOM , IOM ® ® ® -P TE, ITAC , IWE , MUSAC ® ® ...
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... Application – Low Bitrate Communication Systems – Keyless Entry Systems – Remote Control Systems – Alarm Systems – Telemetry Systems Type TDA5251 F1 Data Sheet 2 – I C/3-wire µController Interface s – On-chip low pass channel select filter and data filter with tuneable bandwidth – ...
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... Data Valid Detection, Data Pin . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.18 Sequence Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.19 Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.20 RSSI and Supply Voltage Measurement . . . . . . . . . . . . . . . . . . 3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 LNA and PA Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 RX/TX Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Switch in RX-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Switch in TX-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet st Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . nd I/Q Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . 6 TDA5251 F1 Version 1.1 page ...
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... BER performance depending on Supply Voltage . . . . . . . . . . . 3.11 Default Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.4 Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Test Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet 7 TDA5251 F1 Version 1.1 page ...
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... Provides Clock Out Pin for external microcontroller – Transmit power up to +13 dBm in 50Ω load at 5V supply voltage 2 – I C/3-wire microcontroller interface, working at max. 400kbit/s Data Sheet Product Description = 13mA typ. transmit mode, both supply s 8 TDA5251 F1 Version 1.1 2 C/3-wire 2007-02-26 ...
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... Low Bitrate Communication Systems – Keyless Entry Systems – Remote Control Systems – Alarm Systems – Telemetry Systems – Electronic Metering – Home Automation Systems 1.4 Package Outlines Figure 1-1 PG-TSSOP-38 package outlines Data Sheet Product Description 9 TDA5251 F1 Version 1.1 PG-TSSOP-38.EPS 2007-02-26 ...
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... LNIx GND1 GNDPA PA VCC1 PDN PDP SLC VDD BUSDATA BUSCLK VSS XOUT Figure 2-1 Pin Configuration Data Sheet TDA5251 F1 Version 1.1 Functional Description 38 CI1 37 CI1x 36 CQ1 35 CQ1x 34 CI2 33 CI2x 32 CQ2 31 CQ2x 30 GND 29 RSSI 28 DATA ___ 27 PWDDD 26 CLKDIV ______ 25 RESET ___ 24 EN ...
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... ASKFSK Data Sheet 350 2 200 350 4 11 TDA5251 F1 Version 1.1 Functional Description Function Analog supply (antiparallel diodes between VCC, VCC1, VDD) Bus mode selection (I²C/3 wire bus mode selection) Loop filter and VCO control voltage ASK/FSK- mode switch input 2007-02-26 ...
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... Pin see Pin 8 10 Ω 9 GndPA see Pin 1 12 TDA5251 F1 Version 1.1 Functional Description RX/TX-mode switch input/output RF input to differential Low Noise Amplifier (LNA)) Complementary RF input to differential LNA Ground return for LNA and Power Amplifier (PA) dirver stage Ground return for PA output stage ...
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... Pin 1 15k 350 350 17 see Pin 8 13 TDA5251 F1 Version 1.1 Functional Description Output of the negative peak detector Output of the positive peakdetector Slicer level for the data slicer Digital supply Bus data in/output Bus clock input Ground for digital section ...
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... Vcc-860mV 150µA 125fF ..... 4pF 250fF ..... 8pF see Pin see Pin 22 350 24 14 TDA5251 F1 Version 1.1 Functional Description Crystal oscillator output, can also be used as external reference frequency input. 19 FSK modulation switch ASK modulation/FSK center frequency switch Crystal oscillator ground return 3-wire bus enable input ...
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... Clock output 350 Power Down input (active high), data detect output (active low) 30k 350 TX Data input, RX data output (RX powerdown: pin 28 @ GND) 350 RSSI output S&H 350 16p 37k 15 TDA5251 F1 Version 1.1 Functional Description 2007-02-26 ...
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... Data Sheet see Pin 8 Analog ground Pin for external Capacitor Q-channel, stage 2 Stage1:Vcc-630mV Stage2: Vcc-560mV II Q-channel, stage 2 II I-channel, stage 2 II I-channel, stage 2 II Q-channel, stage 1 II Q-channel, stage 1 II I-channel, stage 1 II I-channel, stage 1 16 TDA5251 F1 Version 1.1 Functional Description 2007-02-26 ...
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... Functional Block Diagram BUSMODE __ EN BUSCLK BUSDATA SLC 31 CQ2x 32 CQ2 33 CI2x 34 CI2 CQ1x 35 36 CQ1 37 CI1x 38 CI1 (digital) (analog) (LNA/PA) Figure 2-2 Main Block Diagram Data Sheet Functional Description TDA5251F1_blockdiagram_aktuell.wmf 17 TDA5251 F1 Version 1.1 2007-02-26 ...
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... IF signal down to zero-IF. These two mixers are driven by a signal that is generated by dividing the local oscillator signal by 4, thus equalling the IF frequency. Data Sheet Description 0= low TX Power, 1= high TX Power Description 0= low Gain, 1= high Gain st Mixer nd I/Q Mixers 18 TDA5251 F1 Version 1.1 Functional Description Default 1 Default 1 2007-02-26 ...
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... The bandwidth of the filters is controlled by the values set in the filter-register. It can be adjusted between 50 and 350kHz in 50kHz steps via the bits the LPF register (subaddress 03H). Data Sheet f osc = = 4 order low pass filters that are used for OP INTERNAL BUS 19 TDA5251 F1 Version 1.1 Functional Description [2 – 1] iq_filter.wmf 2007-02-26 ...
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... Figure 2-4 Quadricorrelator Demodulation Characteristic Data Sheet Functional Description 0 50 100 150 200 250 300 350 f /kHz 20 TDA5251 F1 Version 1.1 Qaudricorrelator.wmf 2007-02-26 ...
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... FSK modulation frequencies. This finetuning of the crystal oscillator allows to eliminate frequency errors due to crystal or component tolerances. Data Sheet OTA Description 0= Lowpass Filter, 1= Peak Detector 21 TDA5251 F1 Version 1.1 Functional Description data_filter.wmf Default 0 2007-02-26 ...
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... FREQUENCY window TH1<T <TH2 GATE RX DATA FSK DATA CONTROL ASK DATA LOGIC BLOCK ENABLE ASK / FSK POWER ON SEQUENCER 22 TDA5251 F1 Version 1.1 Functional Description Operating State Powerdown Mode Device On 2 C/3-wire microcontroller 13.125 MHz XTAL-Osz. WAKEUP LOGIC 32kHz RC-Osz. CLKDiv PwdDD Data ...
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... LOW thus enabling the device. 2.4.15 Bus Interface and Register Definition The TDA5251 supports the I selectable by the BusMode pin (pin 2) as shown in the following table. All bus pins (BusData, BusCLK, EN, BusMode) have a Schmitt-triggered input stage. The BusData pin is bidirectional where the output is open drain driven by an internal 15kΩ pull up resistor. ...
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... To start the communication, the bus master must initiate a start condition (STA), followed by the 8bit chip address. The chip address for the TDA5251 is fixed as „1110000“ (MSB at first). The last bit (LSB=A0) of the chip address byte defines the type of operation to be performed: A0=0, a write operation is selected and A0=1 a read operation is selected ...
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... S3 S2 MSB SUB ADDRESS (READ) LSB 80H, 81H ACK STA DATA OUT FROM SUB ADDRESS TDA5251 F1 Version 1.1 Functional Description Function Chip Address Write Chip Address Read LSB MSB DATA ACK ACK STO LSB MSB DATA ACK D15 ... D8 ACK D7 D6 ... MSB ...
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... ... LSB MSB SPI INTERFACE WAKEUP ON_TIME [16 Bit] OFF_TIME [16 Bit] COUNT_TH1 [16Bit] COUNT_TH2 [16Bit] RSSI_TH3 [8 Bit] 26 TDA5251 F1 Version 1.1 Functional Description DATA IN X...0 (X DATA OUT FROM SUB ADDRESS FILTER LPF [8 Bit] XTAL XTAL_TUNE [16Bit] FSK [16Bit] XTAL_CONFIG [8 Bit] register_overview.wmf ...
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... TX Power, 1= high TX Power 27 TDA5251 F1 Version 1.1 Functional Description Description General definition of status bits Values for FSK-shift Nominal frequency ...
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... D11 0 D10 TDA5251 F1 Version 1.1 Functional Description Sub Address 02H: XTAL_TUNING Function Value Description not used not used not used not used not used not used not used not used not used not used 8pF Setting for nominal 4pF frequency 2pF ...
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... Power Amplifier 1= power down PLL 1= power down XTAL Oscillator Table 2-27 Bit Description data rate < TH1 TH2 < data rate TDA5251 F1 Version 1.1 Functional Description Sub Address 0DH: CLK_DIV Function not used not used DIVMODE_1 DIVMODE_0 CLKDIV_3 CLKDIV_2 CLKDIV_1 CLKDIV_0 Default ...
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... SLAVE MODE (default) MODE_1 = 0 MODE_2 = 0 MODE TIMER MODE MODE_1 = 1 MODE_2 = X MODE_2 SELF POLLING MODE ON_TIME OFF_TIME RX ON: valid Data min. 2.6ms 15µs 30 TDA5251 F1 Version 1.1 Functional Description MODE_1 = 0 MODE_2 = 1 Mode SLAVE MODE TIMER MODE ON_TIME RX ON: invalid Data timing_selfpllmode.wmf 2007-02-26 3_modes.wmf t t ...
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... Window counter into continuous mode (Register 00H, Bit 1). Data Sheet ON_TIME OFF_TIME Register 04H Register 05H 15µs 15µs Amplitude Frequency & RSSI Window DATA on air no DATA on air f 31 TDA5251 F1 Version 1.1 Functional Description ON_TIME Register 04H t t timing_timermode.wmf Frequency data_rate_detect.wmf GATE between 2007-02-26 ...
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... Note required to activate the device for the duration of t Only if this is done the normal operation timing is performed. Data Sheet 0,5*TH1 T 0,5*TH2 GATE TH1 T TH2 GATE RSSI TH3 32 TDA5251 F1 Version 1.1 Functional Description DATA VALID data_valid.wmf Data 28 data_switch.wmf (see Figure 2-15). SYSSU after first power reset. SYSSU 2007-02-26 ...
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... TXSU TXSU 1.1ms 1.1ms t RXSU 2.2ms t DDSU 2.6ms PWDDD = low PD TX activ or RX activ t TXSU 1.1ms t SYSSU 8ms 33 TDA5251 F1 Version 1.1 Functional Description PD RX activ TX activ RX activ * t CLKSU 0.5ms t TXSU 1.1ms t t RXSU RXSU 2.2ms 2.2ms t t DDSU DDSU 2 ...
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... RX is activated. DDSU setup time to enable the power amplifier. TXSU RESET 2 32 kHz ASK/FSK INTERNAL BUS 16 4 BIT COUNTER 32 kHz WINDOW COUNT COMPLETE 34 TDA5251 F1 Version 1.1 Functional Description RC- OSC. XTAL FREQU. SELECT 16 sequencer_raw.wmf CLKDiv 26 clk_div.wmf 2007-02-26 ...
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... Output from Divider (default) 13.125MHz 32kHz Window Count Complete Total Divider Ratio Output Frequency [MHz Input for 6Bit-ADC Vcc / 5 RSSI (default) 35 TDA5251 F1 Version 1.1 Functional Description 6.6 3.3 2.2 1.6 1.3 1.1 0.94 0.82 0.730 (default) 0.66 0.6 0.,55 0.5 0.47 0.44 0.41 2007-02-26 ...
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... ADC- Power Down feedback Bit (D7) and the SELECT feedback Bit (D6) which correspond to the actual measurement. Note: As shown in Section 2.4.18 there is a setup time of 2.6ms after RX activating. Thus the measurement of RSSI voltage does only make sense after this setup time. Data Sheet Functional Description 36 TDA5251 F1 Version 1.1 2007-02-26 ...
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... Switch in RX-Mode The RX/TX-switch is set to the receive mode by either applying a high level or an open to the RX/ TX-jumper on the evalboard or by leaving it open. Then both pin-diodes are not biased and therefore have a high impedance. Data Sheet 37 TDA5251 F1 Version 1.1 Application RX/TX_Switch.wmf 2007-02-26 ...
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... However, the final values of the matching components always have to be found on the board because of the parasitics of the board, which highly influence the matching circuit at RF. Data Sheet 38 TDA5251 F1 Version 1.1 Application RX_Mode.wmf 2007-02-26 ...
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... LOSS 20 * log 1 20 Data Sheet − = 288 MHz 56 MHz 315 MHz = MHz ≈ 315 MHz − log 1 27 39 TDA5251 F1 Version 1.1 Application S11_measured_315.pcx. [3 – – – – 4] 2007-02-26 ...
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... Switch in TX-Mode The evalboard can be set into the TX-Mode by grounding the RX/TX-jumper on the evalboard or programming the TDA5251 to operate in the TX-Mode. If the IC is programmed to operate in the TX-Mode, the RX/TX-pin will act as an open drain output at a logical LOW. Then a DC-current can flow from VCC to GND via L1, L2, D1, R1 and D2. ...
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... TX_Mode_simplified The LNA-matching is RF-grounded now power is lost in the LNA-input. The PA-matching consists of C2, C3 L2, C4 and L1. When designing the matching of the PA, C2 must not be changed anymore because its value is already fixed by the LNA-input-matching. Data Sheet 41 TDA5251 F1 Version 1.1 Application TX_Mode.wmf TX_Mode_simplified.wmf 2007-02-26 ...
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... R Data Sheet Ω . The high efficiency under “critical” operating conditions can practice the RF-saturation voltage of the PA transistor and other . LC 42 TDA5251 F1 Version 1.1 Application Equivalent_power_wmf. [3 – – This is particularly true for low C CE 2007-02-26 ...
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... This is typical for overcritical operation of class C amplifiers. The collector current will show a characteristic dip at the resonance frequency for this type of “overcritical” operation. The depth of this dip will increase with higher values Data Sheet [3 – 11] [3 – 12] 43 TDA5251 F1 Version 1.1 Application > – ...
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... Very short connections must be used. Do not remove the IC or any part of the matching-components! 5. Screw a 50Ohm-dummy-load on the RF-I/O-SMA-connector 6. The TDA5251 has ASK-TX-Mode, Data-Input=LOW sure that your network analyzer is AC-coupled and turn on the power supply of the IC. 8. Measure the S-parameter ...
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... Suppression of spurious harmonics may require some additional filtering within the antenna matching circuit. Both can be seen in Figure 3-10 and Figure 3-11 The total spectrum of the evalboard can be summarized as: Carrier fc +9dBm fc-13.125MHz -74dBm fc+13.125MHz -74dBm nd 2 harmonic -38dBm rd 3 harmonic -40dBm Data Sheet 45 TDA5251 F1 Version 1.1 Application Sparam_measured_315.pcx 2007-02-26 ...
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... Figure 3-10 Transmit Spectrum 3GHz Figure 3-11 Transmit Spectrum 300MHz Data Sheet 46 TDA5251 F1 Version 1.1 Application spectrum_tx_3GMhz.pcx spektrum_tx_3MHz.pcx 2007-02-26 ...
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... Pulling Sensitivity of the crystal is defined as the magnitude of the relative change in frequency relating to the variation of the load capacitor. Data Sheet motional inductance of the crystal motional capacitance of the crystal shunt capacitance of the crystal TDA5251 F1 Version 1.1 Application – 13] [3 – 14] Crystal.wmf 2007-02-26 ...
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... C 1 > > frequency of quartz > L OSC > > The crystal oscillator in the TDA5251 is a NIC (negative impedance converter) oscillator type. The input impedance of this oscillator is a negative impedance in series to an inductance. Therefore the load capacitance of the crystal C capacitance C as shown in formula [3-17]. ...
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... C 1 crystal load capacitance for nominal frequency shunt capacitance of the crystal motional capacitance of the crystal crystal oscillator frequency division ratio of the PLL peak frequency deviation 49 TDA5251 F1 Version 1.1 Application – 17] 2.1µH without pad . v [3 – 18] 2007-02-26 QOSZ_NIC.wmf ...
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... FSK- ASK FSK+ Deviation Deviation Nominal Frequency *N (N: division ratio of the PLL). 0 are necessary. Via internal switches 3 external COSC LOW RF DEV 50 TDA5251 F1 Version 1.1 Application for FSK LOW can be calculated. to realize the necessary frequency 2 in case of ASK- or FSK-modulation – 19] 2007-02-26 free_reg.wmf ...
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... FSK LOW Figure 3-15 FSK modulation Data Sheet and C v2 tune2 ( ) tune2 tune2 tune1 tune2 51 TDA5251 F1 Version 1.1 Application are bypassed. The effective C [3 – 20] is given by – 21 XOUT XIN 21 C tune1 XSWF 20 XSWA tune2 XGND 23 FSK HIGH is given v- QOSC_FSK.wmf 2007-02-26 ...
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... In receive mode a receive frequency offset is necessary as the limiters feedback is AC-coupled. This offset is achieved by setting the oscillator frequency to the FSK HIGH transmit frequency, see Figure 3-15. Data Sheet L -R XOUT XIN XSWF 20 XSWA XGND ⋅ tune2 tune2 v3 52 TDA5251 F1 Version 1.1 Application [3 – 22] C tune1 C tune2 is given by: [3 – 23] 2007-02-26 QOSC_ASK.wmf ...
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... Note: Please keep in mind also to include the Pad parasitics of the circuit board. Data Sheet L XOUT XIN XSWF 20 XSWA XGND 23 Value 4,6 pF FSK-: 2 FSK+&ASK: 2.2pF 1 pF can be calculated tune1 21 ) ⋅ tune2 + tune2 ( tune2 tune2 53 TDA5251 F1 Version 1.1 Application -R C tune1 C C tune2 20 QOSC_parasitics.wmf [3 – 24] [3 – 25] [3 – 25 – 26 2007-02-26 ...
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... FSK LOW – ⋅ – v1 tune1 v+ = --------------------------------------------------------------------- - – – v1 tune1 ⋅ tune1 vm = ------------------------------------------------------------------------ - – tune1 vm 54 TDA5251 F1 Version 1.1 Application for FSK HIGH and – – – – C – – and for vm [3 – 27] [3 – 28] [3 – 29] have to v3 2007-02-26 ...
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... Value 8pF 4pF 2pF 1pF 500fF 250fF 4pF 2pF 1pF 500fF 250fF 125fF 55 TDA5251 F1 Version 1.1 Application Max. Bitrate > 32 kBit/s NRZ > 32 kBit/s NRZ 4 µ kBit/s NRZ 8 µ kBit/s NRZ 12 µ kBit/s NRZ Description Setting for nominal frequency ...
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... Data Sheet . Frequency 315.0 MHz +30 kHz -30 kHz Frequency tolerance @ 315MHz +/- 1.3kHz +/- 2.5kHz +/- 0.6kHz +/- 4.4kHz Frequency tolerance @ 315MHz +/-2.2kHz +/- 2.5kHz +/- 2.5kHz +/- 0.6kHz +/- 7.8kHz 56 TDA5251 F1 Version 1.1 Application Rel. tolerance +/- 4ppm +/- 8ppm +/- 2ppm +/- 14ppm Rel. tolerance +/- 7ppm +/-8ppm +/- 8ppm +/- 2ppm +/- 25ppm 2007-02-26 ...
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... bits of the LPF register (subaddress 03H). Table 3-9 3dB cutoff frequencies I/Q Filter Data Sheet nominal f in kHz -3dB (programmable) not used 350 250 200 150 (default) 100 50 not used 57 TDA5251 F1 Version 1.1 Application resulting effective channel bandwidth in kHz 700 500 400 300 200 100 2007-02-26 ...
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... Data Filter The Data-Filter should be set to values corresponding to the bandwidth of the transmitted Data signal via the bits of the LPF register (subaddress 03H). Data Sheet kHz] effective channel bandwidth -f 3dB IQ Filter 58 TDA5251 F1 Version 1.1 Application 50kHz 100kHz 150kHz 200kHz 250kHz 350kHz iq_filter_curve.wmf f ...
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... I- and Q-channel RSSI-signals are summed to the nominal RSSI signal Filter Filter f g Figure 3-20 Limiter and Pinning Data Sheet D4 nominal Limiter Q Limiter 59 TDA5251 F1 Version 1.1 Application in kHz -3dB 5 7 (default 102 C RSSI 29 RSSI 31 Quadr. 37k Corr. SUM Quadr. Corr. limiter input.wmf 2007-02-26 ...
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... Figure 3-21 Limiter frequency characteristics Data Sheet f3dB upper limit 100 IQ Filter 220 - ll - 470 - 2200 - 3dB IQ Filter 60 TDA5251 F1 Version 1.1 Application Comment setup time not guaranteed setup time not guaranteed Eval Board f f 3dB Limiter limiter_char.wmf 2007-02-26 ...
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... Data Slicer - Slicing Level The data slicer is an analog-to-digital converter necessary to generate a threshold value for the negative comparator input (data slicer). The TDA5251 offers an RC integrator and a peak detector which can be selected via logic. Independent of the choice, the peak detector outputs are always active ...
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... Table 3-13 Sub Address 00H: CONFIG Bit Function D15 SLICER The TDA5251 has two peak detectors built in, one for positive peaks in the data stream and the other for the negative ones. Necessary external components: Data Sheet Description 0= LP, 1= Peak Detector - Pin12: C ...
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... Figure 3-25 Peak Detector timing Data Sheet τ = 100 Ω ⋅ posPkD p τ = 100 Ω ⋅ negPkD τ Signal τ negPkD 63 TDA5251 F1 Version 1.1 Application n posPkD Pos. Peak Detector (pin13) Threshold SLC(pin14) Neg. Peak Detector (pin12) t SLC_PkD.wmf [3 – 32] [3 – 33] PkD_timing.wmf 2007-02-26 ...
Page 64
... L2 3.6.3 Peak Detector - Analog output signal The TDA5251 data output can be digital (pin 28 analog form by using the peak detector output and changing some settings. To get an analog data output the slicer must be set to lowpass mode (Reg. 0, D15 = and the peak detector capacitor at pin has to be changed to a resistor of about 47kOhm. ...
Page 65
... RF power level, which can be set in register 08h in form of the RSSI threshold voltage. Thus for using the data valid detection FSK modulation is recommended. Data Sheet Threshold (pin14) 2,2ms Power Down Power ON 65 TDA5251 F1 Version 1.1 Application PKD_PWDN.wmff Data Signal Peak Detector Power ON PkD_PWDN3.wmf 2007-02-26 ...
Page 66
... Data reset Gate time count comp. comp. start of conversion possible start of next conversion Data reset Gate time count comp. comp. ready* no possible start of next conversion start of conversion because of Single Shot Mode 66 TDA5251 F1 Version 1.1 Application t t reset t count t comp ready* t Frequ_Detect_Timing_continuous.wmf ...
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... We set the thresholds to +-10% and get: T1= 0,225ms and T2= 0,275ms The thresholds TH1 and TH2 are calculated with following formulas Data Sheet T 2*T DATA possible GATE 1 0 2*T2 2*T1 possible GATE ⋅ 0,5ms 2kbit/s f clk [3 – 37] = ⋅ TH1 clk = ⋅ [3 – 38] TH2 TDA5251 F1 Version 1.1 Application window_count_timing.wmf [3 – 36] 2007-02-26 ...
Page 68
... The values have to be written into the D0 to D15 bits of the ON_TIME and OFF_TIME registers (subaddresses 04H and 05H). Data Sheet TH1~ 738= 001011100010 TH2~ 902= 001110000110 RSSI threshold voltage ⋅ 1.2V = 0,055s 32300Hz RC 68 TDA5251 F1 Version 1.1 Application – 39] − – 40] [3 – 41 2007-02-26 ...
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... One possible Solution 15ms 135ms ON OFF Data Sheet b b Data Data Data Data 50ms 50ms 400ms Preamble Data Syncronisation Preamble 69 TDA5251 F1 Version 1.1 Application t [ms] t [ms] t [ms] data_timing011.wmf 2007-02-26 ...
Page 70
... Receiver until Data completed Interrupt due PwdDD Data Data Data 50ms 15ms 135ms µP enables Receiver until Data completed Interrupt due PwdDD ... Receiver enabled 70 TDA5251 F1 Version 1.1 Application Data t [ms] Data t [ms] Data t [ms] data_timing021.wmf 2007-02-26 ...
Page 71
... The resulting I/Q signals are applied to the SMIQ to generate a ASK (OOK) spectrum at the desired RF frequency. Data is demodulated by the TDA5251 and then sent back to the AMIQ to be compared with the originally sent data. The bit error rate is calculated by the bit error rate equipment inside the AMIQ. ...
Page 72
... Due to the wide supply voltage range of this transeiver chip also the sensitivity behaviour over this parameter is documented is the subsequent graph. Figure 3-35 BER supply voltage Please notice the tiny sensitivity changes of less than 1dB, when variing the supply voltage. Data Sheet 72 TDA5251 F1 Version 1.1 Application BER_VCC.wmf 2007-02-26 ...
Page 73
... Operating Mode Data Sheet Value IFX-Board 150kHz 7kHz 470Hz 47nF RC 10nF 4.5pF 315MHz 2.5pF +30kHz 1.5pF -30kHz HIGH HIGH +10dBm 2.6ms 2.2nF RSSI 10ms 100ms 0.73MHz 0.73MHz - - bipolar off - Jumper - Jumper PWDN Jumper removed Slave 73 TDA5251 F1 Version 1.1 Application Comment 2007-02-26 ...
Page 74
... ESD-HBM V -500 ESD-HBM Symbol Limit Values min max V 2 312 325 RX f 312 325 TX 74 TDA5251 F1 Version 1.1 Reference Unit Remarks max 5.8 V +125 °C +150 °C 114 K/W +1.5 kV CDM according EIA/JESD22-C101 +2.0 kV HBM according EIA/JESD22-A114-B (1.5k Ω , 100pF) +500 V ...
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... RSSI t 3.35 Data_Valid P -48dBm 1dB P -32dBm 1dB_low V 50 BL_1MHz P -102 LO 75 TDA5251 F1 Version 1.1 Reference = 2.1 ... 5.5 V VCC Unit Test Conditions mA 3V, FSK, Default mA 5V, FSK, Default mA 3V, ASK, Default mA 5V, ASK, Default dBm FSK@30kHz, 4kBit/s Manch. Data, Default 7kHz datafilter, 50kHz IQ filter dBm ASK, 4kBit/s Manch ...
Page 76
... TXSU P -75 clock P -74 1st P -38 2nd P -40 3rd 76 TDA5251 F1 Version 1.1 Reference = 2.1 ... 5.5 V VCC Unit Test Conditions mA 2.1V, high power mA 3V, high power mA 5V, high power dBm 2.1V, high power dBm 3V, high power dBm 5V, high power mA 2 ...
Page 77
... V 0.5 0.67 1.6 cc-tune,RX V 0.5 0.86 1.6 cc-tune,TX 77 TDA5251 F1 Version 1.1 Reference = 2.1 ... 5.5 V Test Conditions uA 3V, 32kHz clock on uA 5V, 32kHz clock on uA 3V, CONFIG9=1 uA 5V, CONFIG9=1 kHz ms IFX Board with Crystal Q1 as specified in Section 4 ...
Page 78
... BUF BusData BusCLK H D. HIG H EN pulsed or t mandatory low SU. ENAS DA t SU. ENAS DA 2 Figure 4 Bus Timing 3-wire Bus Timing B U S_M S_E Figure 4-2 3-wire Bus Timing Data Sheet HD. DAT .DAT SU. STA TDA5251 F1 Version 1.1 Reference D. SU SU. ENA SDA 2007-02-26 ...
Page 79
... V OH Vdd 0 400 SLC t 1.3 BUF t 0.6 HO.STA 79 TDA5251 F1 Version 1.1 Reference = 2.1 ... 5.5 V Unit Test Conditions PRBS9, Manch.@+9dBm PRBS9, Manch.@+9dBm @30kHz dev. PRBS9, Manch. PRBS9, Manch. @30kHz dev @Vdd=3V V Isink=800uA Isink=3mA ns @Vdd=3V ns load 10pF V load 10pF V I ...
Page 80
... LOW t 0.6 HIGH t 0.6 SU.STA t 0 HD.DAT t 100 SU.DAT 20+ 300 0.6 SU.STO C 400 b 0.6 SU.SCLE N t 0.6 WHEN 80 TDA5251 F1 Version 1.1 Reference = 2.1 ... 5.5 V Unit Test Conditions µs V =5V dd µ µs only I C mode µs only I C mode V ...
Page 81
... Test Circuit The device performance parameters marked with evaluation board (IFX board). Figure 4-3 Schematic of the Evaluation Board Data Sheet X in Section 4.1.3 were measured on an Infineon 81 TDA5251 F1 Version 1.1 Reference TDA5250_v42.schematic.pdf 2007-02-26 ...
Page 82
... In case of reproduction please bear in mind that this may not be suitable for all automatic soldering processes. Note 2: Please keep in mind not to layout the CLKDIV line directly in the neighborhood of the crystal and the associated components. Note 3: The opto part (X4) should be supplied by connecting to X3. Data Sheet 82 TDA5251 F1 Version 1.1 Reference TDA5250_v42_layout.pdf 2007-02-26 ...
Page 83
... TDA5251 F1 Version 1.1 Reference Tolerance +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% ...
Page 84
... SIMID 0603-C (EPCOS) 47nH SIMID 0603-C (EPCOS) 56nH SIMID 0603-C (EPCOS) TDA5251 F1 PTSSOP38 ILQ74 SFH6186 13.125MHz Telcona: C0=1,8pF 1-pol. BC847B SOT-23 (Infineon) BAR63-02W SCD-80 (Infineon) SMA-socket SubD 25p. 84 TDA5251 F1 Version 1.1 Reference Tolerance 0603 +/-10% 0603 +/-1% 0603 +/-0,1pF 0603 +/-1% 0603 +/-10% 0603 +/-10% 0603 +/-10% 0603 ...
Page 85
... Default Setup (without internal tuning & without Pin21 usage Table 3-9 3dB cutoff frequencies I/Q Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3-10 3dB cutoff frequencies Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3-11 Limiter Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3-12 Sub Address 00H: CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet 85 TDA5251 F1 Version 1.1 page 11 page 18 page 18 page 21 page 22 page 23 page 25 page 25 page 25 ...
Page 86
... Table 4-3 AC/DC Characteristics with °C, VVCC = 2.1 ... 5 Table 4-4 AC/DC Characteristics with °C, VVCC = 2.1 ... 5 Table 4-5 Digital Characteristics with °C, VVdd = 2.1 ... 5 Table 4-6 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet 86 TDA5251 F1 Version 1.1 page 62 page 73 page 74 page 74 page 75 page 77 page 79 page 83 ...
Page 87
... IQ Filter and frequency characteristics of the receive system page Figure 3-20 Limiter and Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Figure 3-21 Limiter frequency characteristics page Figure 3-22 Typ. RSSI Level (Eval Board) @ page Figure 3-23 Slicer Level using RC Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Figure 3-24 Slicer Level using Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . page Data Sheet 87 TDA5251 F1 Version 1 ...
Page 88
... Figure 3-34 BER Test Setup page Figure 3-35 BER supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Figure 4-1 I2C Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Figure 4-2 3-wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Figure 4-3 Schematic of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . page Figure 4-4 Layout of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Data Sheet 88 TDA5251 F1 Version 1 ...