ATA5771-PXQW Atmel, ATA5771-PXQW Datasheet - Page 135

XMITTR UHF ASK/FSK 868MHZ 24VQFN

ATA5771-PXQW

Manufacturer Part Number
ATA5771-PXQW
Description
XMITTR UHF ASK/FSK 868MHZ 24VQFN
Manufacturer
Atmel
Datasheet

Specifications of ATA5771-PXQW

Frequency
868MHz ~ 928MHz
Modulation Or Protocol
UHF
Power - Output
8dBm
Voltage - Supply
2 V ~ 4 V
Current - Transmitting
9.8mA
Data Interface
PCB, Surface Mount
Memory Size
4kB Flash, 256B EEPROM, 256B SRAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
Processor Series
ATA5x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
4 KB
Data Ram Size
256 B
Interface Type
SPI, USI
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Applications
-
Sensitivity
-
Data Rate - Maximum
-
Current - Receiving
-
Lead Free Status / Rohs Status
 Details

Available stocks

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Part Number:
ATA5771-PXQW
Manufacturer:
ATMEL
Quantity:
218
9137E–RKE–12/10
• Bit 6 – USIOIE: Counter Overflow Interrupt Enable
Setting this bit to one enables the Counter Overflow interrupt. If there is a pending interrupt
when the USIOIE and the Global Interrupt Enable Flag is set to one, this will immediately be
executed. See the USIOIF bit description in
further details.
• Bit 5..4 – USIWM1..0: Wire Mode
These bits set the type of wire mode to be used. Basically only the function of the outputs are
affected by these bits. Data and clock inputs are not affected by the mode selected and will
always have the same function. The counter and Shift Register can therefore be clocked
externally, and data input sampled, even when outputs are disabled. The relations between
USIWM1..0 and the USI operation is summarized in
Table 4-44.
Note:
USIWM1
0
0
1
1
1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respec-
tively to avoid confusion between the modes of operation.
USIWM0
Relations between USIWM1..0 and the USI Operation
0
1
0
1
Description
Outputs, clock hold, and start detector disabled. Port pins operates as
normal.
Three-wire mode. Uses DO, DI, and USCK pins.
The Data Output (DO) pin overrides the corresponding bit in the PORT
Register in this mode. However, the corresponding DDR bit still controls the
data direction. When the port pin is set as input the pins pull-up is controlled
by the PORT bit.
The Data Input (DI) and Serial Clock (USCK) pins do not affect the normal
port operation. When operating as master, clock pulses are software
generated by toggling the PORT Register, while the data direction is set to
output. The USITC bit in the USICR Register can be used for this purpose.
Two-wire mode. Uses SDA (DI) and SCL (USCK) pins
The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-directional
and uses open-collector output drives. The output drivers are enabled by
setting the corresponding bit for SDA and SCL in the DDR Register.
When the output driver is enabled for the SDA pin, the output driver will
force the line SDA low if the output of the Shift Register or the corresponding
bit in the PORT Register is zero. Otherwise the SDA line will not be driven
(i.e., it is released). When the SCL pin output driver is enabled the SCL line
will be forced low if the corresponding bit in the PORT Register is zero, or by
the start detector. Otherwise the SCL line will not be driven.
The SCL line is held low when a start detector detects a start condition and
the output is enabled. Clearing the Start Condition Flag (USISIF) releases
the line. The SDA and SCL pin inputs is not affected by enabling this mode.
Pull-ups on the SDA and SCL port pin are disabled in Two-wire mode.
Two-wire mode. Uses SDA and SCL pins.
Same operation as for the Two-wire mode described above, except that the
SCL line is also held low when a counter overflow occurs, and is held low
until the Counter Overflow Flag (USIOIF) is cleared.
“USISR – USI Status Register” on page 133
Table
Atmel ATA5771/73/74
4-44.
(1)
.
135
for

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