ATA5771-PXQW Atmel, ATA5771-PXQW Datasheet - Page 37

• Manufacturer Part Number: ATA5771-PXQW
• Description: XMITTR UHF ASK/FSK 868MHZ 24VQFN
• Manufacturer: Atmel

Specifications of ATA5771-PXQW

• Frequency: 868MHz ~ 928MHz
• Modulation Or Protocol: UHF
• Power - Output: 8dBm
• Voltage - Supply: 2 V ~ 4 V
• Current - Transmitting: 9.8mA
• Data Interface: PCB, Surface Mount
• Memory Size: 4kB Flash, 256B EEPROM, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Processor Series: ATA5x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 4 KB
• Data Ram Size: 256 B
• Interface Type: SPI, USI
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

4.9.7
9137E–RKE–12/10
External Clock
To drive the device from an external clock source, CLKI should be driven as shown in
4-12. To run the device on an external clock, the CKSEL Fuses must be programmed to
“0000”.
Figure 4-12. External Clock Drive Configuration
When this clock source is selected, start-up times are determined by the SUT Fuses as shown
in
Table 4-10.
When applying an external clock, it is required to avoid sudden changes in the applied clock
frequency to ensure stable operation of the MCU. A variation in frequency of more than 2%
from one clock cycle to the next can lead to unpredictable behavior. It is required to ensure
that the MCU is kept in Reset during such changes in the clock frequency.
Note that the System Clock Prescaler can be used to implement run-time changes of the inter-
nal clock frequency while still ensuring stable operation. See to
Prescaler” on page 38
SUT1..0
Table
00
01
10
11
4-10.
Power-down and Power-save
Start-up Times for the External Clock Selection
Start-up Time from
for details.
6 CK
6 CK
6 CK
EXTERNAL
SIGNAL
CLOCK
Additional Delay from
Reserved
14CK + 64 ms
14CK + 4 ms
CLKI
GND
Reset
Atmel ATA5771/73/74
14CK
Section 4.9.9 “System Clock
BOD enabled
Fast rising power
Slowly rising power
Recommended Usage
Figure
37