ATA5771-PXQW Atmel, ATA5771-PXQW Datasheet - Page 38

XMITTR UHF ASK/FSK 868MHZ 24VQFN

ATA5771-PXQW

Manufacturer Part Number
ATA5771-PXQW
Description
XMITTR UHF ASK/FSK 868MHZ 24VQFN
Manufacturer
Atmel
Datasheet

Specifications of ATA5771-PXQW

Frequency
868MHz ~ 928MHz
Modulation Or Protocol
UHF
Power - Output
8dBm
Voltage - Supply
2 V ~ 4 V
Current - Transmitting
9.8mA
Data Interface
PCB, Surface Mount
Memory Size
4kB Flash, 256B EEPROM, 256B SRAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
Processor Series
ATA5x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
4 KB
Data Ram Size
256 B
Interface Type
SPI, USI
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Applications
-
Sensitivity
-
Data Rate - Maximum
-
Current - Receiving
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATA5771-PXQW
Manufacturer:
ATMEL
Quantity:
218
4.9.8
4.9.9
4.9.9.1
38
Atmel ATA5771/73/74
128 kHz Internal Oscillator
System Clock Prescaler
Switching Time
The 128kHz internal Oscillator is a low power Oscillator providing a clock of 128kHz. The fre-
quency is nominal at 3V and 25°C. This clock may be select as the system clock by
programming the CKSEL Fuses to “0100”.
When this clock source is selected, start-up times are determined by the SUT Fuses as shown
in
Table 4-11.
The Atmel
CLKPR. This feature can be used to decrease power consumption when the requirement for
processing power is low. This can be used with all clock source options, and it will affect the
clock frequency of the CPU and all synchronous peripherals. clk
are divided by a factor as shown in
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occur in the clock system and that no intermediate frequency is higher than neither
the clock frequency corresponding to the previous setting, nor the clock frequency corre-
sponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the
state of the prescaler – even if it were readable, and the exact time it takes to switch from one
clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before
the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1
is the previous clock period, and T2 is the period corresponding to the new prescaler setting.
SUT1..0
Table
00
01
10
11
4-11.
®
ATtiny44V system clock can be divided by setting the Clock Prescale Register –
Power-down and Power-save
Start-up Times for the 128 kHz Internal Oscillator
Start-up Time from
6 CK
6 CK
6 CK
Table 4-12 on page
Additional Delay from
Reserved
14CK + 64 ms
14CK + 4 ms
Reset
14CK
40.
I/O
, clk
BOD enabled
Fast rising power
Slowly rising power
ADC
Recommended Usage
, clk
CPU
9137E–RKE–12/10
, and clk
FLASH

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