ATA5771-PXQW Atmel, ATA5771-PXQW Datasheet - Page 50

• Manufacturer Part Number: ATA5771-PXQW
• Description: XMITTR UHF ASK/FSK 868MHZ 24VQFN
• Manufacturer: Atmel

Specifications of ATA5771-PXQW

• Frequency: 868MHz ~ 928MHz
• Modulation Or Protocol: UHF
• Power - Output: 8dBm
• Voltage - Supply: 2 V ~ 4 V
• Current - Transmitting: 9.8mA
• Data Interface: PCB, Surface Mount
• Memory Size: 4kB Flash, 256B EEPROM, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Processor Series: ATA5x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 4 KB
• Data Ram Size: 256 B
• Interface Type: SPI, USI
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

4.11.3
4.11.4
4.11.4.1
50
Atmel ATA5771/73/74
Watchdog Timer
Timed Sequences for Changing the Configuration of the Watchdog Timer
Safety Level 1
The Watchdog Timer is clocked from an On-chip Oscillator which runs at 128kHz. By control-
ling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in
Table 4-18 on page
The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten dif-
ferent clock cycle periods can be selected to determine the reset period. If the reset period
expires without another Watchdog Reset, the ATtiny44V resets and executes from the Reset
Vector. For timing details on the Watchdog Reset, refer to
The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This
can be very helpful when using the Watchdog to wake-up from Power-down.
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period,
two different safety levels are selected by the fuse WDTON as shown in
tion 4.11.4 “Timed Sequences for Changing the Configuration of the Watchdog Timer” on
page 50
Table 4-16.
Figure 4-19. Watchdog Timer
The sequence for changing configuration differs slightly between the two safety levels. Sepa-
rate procedures are described for each level.
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE
bit to one without any restriction. A timed sequence is needed when disabling an enabled
Watchdog Timer. To disable an enabled Watchdog Timer, the following procedure must be
followed:
WDTON
Unprogrammed
Programmed
for details.
WDT Configuration as a Function of the Fuse Settings of WDTON
53. The WDR – Watchdog Reset – instruction resets the Watchdog Timer.
Safety
Level
1
2
WATCHDOG
OSCILLATOR
RESET
128 kHz
WDP0
WDP1
WDP2
WDP3
WDE
WDT Initial
State
Disabled
Enabled
Always enabled
How to Disable the
WDT
Timed sequence
MCU RESET
PRESCALER
WATCHDOG
Table 4-18 on page
How to Change
Time-out
No limitations
Timed sequence
Table 4-16
53.
9137E–RKE–12/10
See
Sec-