ATA5771-PXQW Atmel, ATA5771-PXQW Datasheet - Page 52

• Manufacturer Part Number: ATA5771-PXQW
• Description: XMITTR UHF ASK/FSK 868MHZ 24VQFN
• Manufacturer: Atmel

Specifications of ATA5771-PXQW

• Frequency: 868MHz ~ 928MHz
• Modulation Or Protocol: UHF
• Power - Output: 8dBm
• Voltage - Supply: 2 V ~ 4 V
• Current - Transmitting: 9.8mA
• Data Interface: PCB, Surface Mount
• Memory Size: 4kB Flash, 256B EEPROM, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Processor Series: ATA5x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 4 KB
• Data Ram Size: 256 B
• Interface Type: SPI, USI
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

4.11.5.2
52
Atmel ATA5771/73/74
WDTCSR – Watchdog Timer Control and Status Register
• Bit 7 – WDIF: Watchdog Timeout Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is con-
figured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit
in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.
• Bit 6 – WDIE: Watchdog Timeout Interrupt Enable
When this bit is written to one, WDE is cleared, and the I-bit in the Status Register is set, the
Watchdog Time-out Interrupt is enabled. In this mode the corresponding interrupt is executed
instead of a reset if a timeout in the Watchdog Timer occurs.
If WDE is set, WDIE is automatically cleared by hardware when a time-out occurs. This is use-
ful for keeping the Watchdog Reset security while using the interrupt. After the WDIE bit is
cleared, the next time-out will generate a reset. To avoid the Watchdog Reset, WDIE must be
set after each interrupt.
Table 4-17.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will
not be disabled. Once written to one, hardware will clear this bit after four clock cycles. See
the description of the WDE bit for a Watchdog disable procedure. This bit must also be set
when changing the prescaler bits. See
Configuration of the Watchdog Timer” on page
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is writ-
ten to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the
WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure
must be followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be writ-
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm
described above. See
Watchdog Timer” on page
Bit
0x21 (0x41)
Read/Write
Initial Value
WDE
ten to WDE even though it is set to one before the disable operation starts.
0
0
1
1
Watchdog Timer Configuration
WDIF
R/W
WDIE
7
0
0
1
0
1
Section 4.11.4 “Timed Sequences for Changing the Configuration of the
WDIE
R/W
6
0
Watchdog Timer State
Stopped
Running
Running
Running
50.
WDP3
R/W
5
0
Section 4.11.4 “Timed Sequences for Changing the
WDCE
R/W
4
0
50.
WDE
R/W
X
3
WDP2
R/W
2
0
Action on Time-out
None
Interrupt
Reset
Interrupt
WDP1
R/W
1
0
WDP0
R/W
0
0
9137E–RKE–12/10
WDTCSR