ATA5771-PXQW Atmel, ATA5771-PXQW Datasheet - Page 57

XMITTR UHF ASK/FSK 868MHZ 24VQFN

ATA5771-PXQW

Manufacturer Part Number
ATA5771-PXQW
Description
XMITTR UHF ASK/FSK 868MHZ 24VQFN
Manufacturer
Atmel
Datasheet

Specifications of ATA5771-PXQW

Frequency
868MHz ~ 928MHz
Modulation Or Protocol
UHF
Power - Output
8dBm
Voltage - Supply
2 V ~ 4 V
Current - Transmitting
9.8mA
Data Interface
PCB, Surface Mount
Memory Size
4kB Flash, 256B EEPROM, 256B SRAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
Processor Series
ATA5x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
4 KB
Data Ram Size
256 B
Interface Type
SPI, USI
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Applications
-
Sensitivity
-
Data Rate - Maximum
-
Current - Receiving
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATA5771-PXQW
Manufacturer:
ATMEL
Quantity:
218
4.13
4.13.1
9137E–RKE–12/10
External Interrupts
Pin Change Interrupt Timing
The External Interrupts are triggered by the INT0 pin or any of the PCINT11..0 pins. Observe
that, if enabled, the interrupts will trigger even if the INT0 or PCINT11..0 pins are configured as
outputs. This feature provides a way of generating a software interrupt. Pin change 0 inter-
rupts PCI0 will trigger if any enabled PCINT7..0 pin toggles. Pin change 1 interrupts PCI1 will
trigger if any enabled PCINT11..8 pin toggles. The PCMSK0 and PCMSK1 Registers control
which pins contribute to the pin change interrupts. Pin change interrupts on PCINT11..0 are
detected asynchronously. This implies that these interrupts can be used for waking the part
also from sleep modes other than Idle mode.
The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as
indicated in the specification for the MCU Control Register – MCUCR. When the INT0 interrupt
is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is
held low. Note that recognition of falling or rising edge interrupts on INT0 requires the pres-
ence of an I/O clock, described in
32. Low level interrupt on INT0 is detected asynchronously. This implies that this interrupt can
be used for waking the part also from sleep modes other than Idle mode. The I/O clock is
halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no
interrupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as
described in
An example of timing of a pin change interrupt is shown in
Figure 4-20. Timing of pin change interrupts
Section 4.9 “System Clock and Clock Options” on page
pcint_setflag
pcint_in_(0)
PCINT(0)
pcint_syn
pin_sync
pin_lat
PCINT(0)
PCIF
clk
clk
LE
pin_lat
D
Section 4.9.1 “Clock Systems and their Distribution” on page
Q
pin_sync
PCINT(0) in PCMSK(x)
pcint_in_(0)
0
x
Atmel ATA5771/73/74
clk
Figure
pcint_syn
4-20.
32.
pcint_setflag
PCIF
57

Related parts for ATA5771-PXQW