ATA5771-PXQW Atmel, ATA5771-PXQW Datasheet - Page 78

• Manufacturer Part Number: ATA5771-PXQW
• Description: XMITTR UHF ASK/FSK 868MHZ 24VQFN
• Manufacturer: Atmel

Specifications of ATA5771-PXQW

• Frequency: 868MHz ~ 928MHz
• Modulation Or Protocol: UHF
• Power - Output: 8dBm
• Voltage - Supply: 2 V ~ 4 V
• Current - Transmitting: 9.8mA
• Data Interface: PCB, Surface Mount
• Memory Size: 4kB Flash, 256B EEPROM, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Processor Series: ATA5x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 4 KB
• Data Ram Size: 256 B
• Interface Type: SPI, USI
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

4.15.4
78
Atmel ATA5771/73/74
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
4-27
Figure 4-27. Counter Unit Block Diagram
Signal description (internal signals):
Depending of the mode of operation used, the counter is cleared, incremented, or decre-
mented at each timer clock (clk
source, selected by the Clock Select bits (CS02:0). When no clock source is selected
(CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU,
regardless of whether clk
counter clear or count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located
in the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the
Timer/Counter Control Register B (TCCR0B). There are close connections between how the
counter behaves (counts) and how waveforms are generated on the Output Compare output
OC0A. For more details about advanced counting sequences and waveform generation, see
Section 4.15.7 “Modes of Operation” on page
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected
by the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.
shows a block diagram of the counter and its surroundings.
count
direction
clear
clk
top
bottom
Tn
DATA BUS
TCNTn
T0
is present or not. A CPU write overrides (has priority over) all
Increment or decrement TCNT0 by 1.
Select between increment and decrement.
Clear TCNT0 (set all bits to zero).
Timer/Counter clock, referred to as clk
Signalize that TCNT0 has reached maximum value.
Signalize that TCNT0 has reached minimum value (zero).
T0
). clk
direction
count
clear
T0
bottom
can be generated from an external or internal clock
Control Logic
81.
top
TOVn
(Int.Req.)
clk
Tn
Clock Select
( From Prescaler )
Detector
Edge
T0
in the following.
9137E–RKE–12/10
Tn
Table