ATA5428-PLQW Atmel, ATA5428-PLQW Datasheet
ATA5428-PLQW
Specifications of ATA5428-PLQW
ATA5428-PLQHCT
ATA5428-PLQWCT
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ATA5428-PLQW Summary of contents
Page 1
... Adjustable Output Power dBm Adjusted and Stabilized with External Resistor • ESD Protection at all Pins (1.5 kV HBM, 200V MM FCDM) • Supply Voltage Range: 2.4V to 3.6V or 4.4V to 6.6V • Temperature Range: –40°C to +85°C • Small QFN48 Package UHF ASK/FSK Transceiver ATA5423 ATA5425 ATA5428 ATA5429 4841D–WIRE–10/07 ...
Page 2
... Less Demanding Specification for the Microcontroller Due to Handling of Power-down Mode, Delivering of Clock, Reset, Low Battery Indication and Complete Handling of Receive/Transmit Protocol and Polling • Single-ended Design with High Isolation of PLL/VCO from PA and the Power Supply Allows a Loop Antenna in the Remote Control Unit to Surround the Whole Application ATA5423/ATA5425/ATA5428/ATA5429 2 4841D–WIRE–10/07 ...
Page 3
... The device supports data rates of 1 Kbit Kbit/s (FSK) and 1 Kbit Kbit/s (ASK) in Manchester, Bi-phase and other codes in transparent mode. The ATA5428 can be used in the 431.5 MHz to 436.5 MHz and in the 862 MHz to 872 MHz bands, the ATA5423 in the 312.5 MHz to 317 ...
Page 4
... Figure 1-1. System Block Diagram Antenna Matching/ RF Switch Figure 1-2. Pinning QFN48 ATA5423/ATA5425/ATA5428/ATA5429 4 ATA5423/ATA5425/ATA5428/ATA5429 RF Transceiver Digital Control Logic XTO RF_IN 433_N868 6 ATA5423/ATA5425 NC 7 ATA5428/ATA5429 R_PWR 8 PWR_H 9 RF_OUT Power Supply ATmega 44/88/168 Microcontroller interface RSSI CS 35 DEM_OUT 34 SCK 33 32 SDI_TMDI SDO_TMDO 31 CLK ...
Page 5
... ATA5423/ATA5425/ATA5428/ATA5429 Pin Description Symbol Function NC Not connected NC Not connected NC Not connected RF_IN RF input NC Not connected 433_N868 Selects RF input/output frequency range NC Not connected R_PWR Resistor to adjust output power PWR_H Pin to select output power RF_OUT RF output NC Not connected NC Not connected ...
Page 6
... CLK N_RESET IRQ Microcontroller interface CS SCK SDI_TMDI SDO_TMDO VSINT ATA5423/ATA5425/ATA5428/ATA5429 6 Pin Description (Continued) Symbol Function T4 Key input 4 (can also be used to switch on the system (active low)) T3 Key input 3 (can also be used to switch on the system (active low)) T2 Key input 2 (can also be used to switch on the system (active low)) ...
Page 7
... The ATA5423/ATA5425/ATA5428/ATA5429 provides sufficient isolation and robust pulling behavior of internal circuits from the supply voltage as well as an integrated VCO inductor to allow this. ...
Page 8
... RF_OUT to about 10 dBm Since and C together form a low-pass filter, which is needed to filter out 2.2 µF has to be connected to VSOUT in any case DEM_OUT NC RF_IN NC 433_N868 SDO_TMDO ATA5423/ATA5425 NC ATA5428/ATA5429 R_PWR PWR_H RF_OUT 4.75V to 5.25V = 4.75V to 5.25V Base-station Application (5V). The CC and C are 2.2 µF supply block- ...
Page 9
... A load capacitor for the crystal typically 22 k and sets the output power to about 5.5 dBm RF_IN NC 433_N868 ATA5423/ATA5425 R ATA5428/ATA5429 NC 1 R_PWR PWR_H RF_OUT Lithium cell + Lithium cell are 2.2 µF supply blocking capacitors for the inter- ...
Page 10
... In receive mode the LNA pre-amplifies the received signal which is converted down to 226 kHz (ATA5423/ATA5428) and 235 kHz (ATA5425/ATA5429), filtered and amplified before it is fed into an FSK/ASK demodulator, data filter, and data slicer. The RSSI (Received Signal Strength Indicator) signal and the raw digital output signal of the demodulator are available at the pins RSSI and DEM_OUT ...
Page 11
... Figure 3-1 12. These measurements were done with induc- Table 3-2, resulting in estimated matching losses of and the matching loss with 10 log Table 3-3 Table 9-3 on page ATA5423/ATA5425 ATA5428/ATA5429 4 RF_IN and with the - loss and Table 3 ...
Page 12
... IF filter bandwidth of the receiver. sensitivity at 433.92 MHz/FSK/20 Kbit/s/ 16 kHz/Manchester versus the frequency offset between transmitter and receiver with T VS1 = VS2 = 2.4V, 3.0V and 3.6V. ATA5423/ATA5425/ATA5428/ATA5429 12 Input Matching /MHz ...
Page 13
... RX mode. For that purpose, an automatic mode is also available. This automatic mode switches to IDLE mode and back into RX mode every time a bit error occurs. Control Logic” on page 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 Measured Sensitivity 433.92 MHz/FSK/20 Kbit/s/±16 kHz/Manchester versus Frequency Offset, Temperature and Supply Voltage -110 ...
Page 14
... BER is higher than 10 page 11 -103 dBm + –47 dBm. These values, together with the good intermodulation perfor- mance, avoid the need for a SAW filter in the remote control unit application. ATA5423/ATA5425/ATA5428/ATA5429 14 Table 7-7 on page 39 and Table 7-10 on page ± ...
Page 15
... BER is higher than higher than –100 dBm which is –100 dBm + –41 dBm. Table 3-6 on page 16 other frequencies. Note that sometimes the blocking is measured relative to the sensitivity level (dBS) instead of the carrier (dBC). 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 Narrow Band 3 dB Blocking Characteristic at 433.92 MHz ...
Page 16
... Table 3-6. The ATA5423/ATA5425/ATA5428/ATA5429 can also receive FSK and ASK modulated signals if they are much higher than the I1dBCP. It can typically receive useful signals at 10 dBm. This is often referred to as the nonlinear dynamic range which is the maximum to minimum receiving signal and is 116 dB for 20 Kbit/s Manchester. This value is useful if two transceivers have to communicate and are very close to each other ...
Page 17
... IF filter. The demodulator, data filter and data slicer are important, in that case. The data filter of the ATA5423/ATA5425/ATA5428/ATA5429 implies a quasi-peak detector. This results in a good suppression of the above mentioned disturbers and exhibits a good carrier to Gaussian noise performance ...
Page 18
... FSK transmission and the power amplifier is switched on and off to perform the modulation. ulation with pseudo-random data with 20 Kbit/s/±16.17 kHz/Manchester and 5 dBm output power. ATA5423/ATA5425/ATA5428/ATA5429 18 is the reference frequency FREF for the synthesizer. XTO Figure 3-9 on page Table 4-1 on page Figure 2 ...
Page 19
... Unmodulated TX Spectrum 433.92 MHz – 16.17 kHz (f Ref 10 dB Samp Log 10 dB/ VAvg Center 433.92 MHz Res BW 10 kHz 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 Atten 20 dB VBW 100 kHz ) FSK_L Atten 20 dB VBW 10 kHz Span 30 MHz Sweep 7.5 ms (401 pts) Span 1 MHz Sweep 27.5 ms (401 pts) 19 ...
Page 20
... There must also be a low resistive DC path to AVCC to deliver the DC current of the power amplifier's last stage. The matching of the PA output was done with the circuit shown in 3-10 on page 21 ments may be necessary to compensate for individual board layouts. ATA5423/ATA5425/ATA5428/ATA5429 20 Atten 20 dB VBW 10 kHz ...
Page 21
... Characteristics: General” on page (10 nF) has to be placed close to the matching network 2 AVCC OUT VPWR_H 100% = 38.6% in this case results in 9.1% less cur- log(1.091) = 0.38 dB less output power 22. Looking to the 433.92 MHz/11 dBm case 67 ATA5423/ATA5425/ ATA5428/ATA5429 10 RF_OUT 8 R_PWR 9 PWR_H ...
Page 22
... Table 3- ATA5423/ATA5425/ATA5428/ATA5429 22 0.4 56 5 ...
Page 23
... The principal switching operation is described here according to the application of Figure 2-1 on page Table 3-10. Figure 3-11. Equivalent Circuit of the Switch 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 shows the relative changes of the output power of a typical device compared to Table 3-7 on page 22 over temperature and supply voltage have shown about the same Table 3-9. Measurements of Typical Output Power Relative to 3V/25° ...
Page 24
... RX mode; hence the antenna bandwidth is higher than in TX mode. Table 3-11. Note that if matching like in Q > 70 should be used for L dominant. The RX and TX losses will be in the range of 1.0 dB there. ATA5423/ATA5425/ATA5428/ATA5429 24 has an impedance of about 50 locking from the transmission line into the loop ...
Page 25
... P ±50 ppm. Since typical crystals have less than ±50 ppm tolerance at 25°C, the compensation is not criti- cal, and can in both cases be done with the ±150 ppm. 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 is the reference frequency FREF for the fractional-N synthesizer. When XTO and Table 7-10) ...
Page 26
... VSOUT and DVCC voltage also have to be fulfilled (see To save current in IDLE and Sleep modes, the load capacitors are partially switched off in these modes with S1 and S2, as seen recommended to use a crystal with 1 2.2 pF. 0 Lower values of C higher values of C ATA5423/ATA5425/ATA5428/ATA5429 26 Lmin ...
Page 27
... To find the right values used in control registers 2 and 3 (see relationship between f content, the frequency at pin CLK as well as the output frequency at RF_OUT in ASK mode can be measured, then the FREQ value can be calculated according exactly the desired radio frequency. RF 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 XTO Block Diagram XTAL1 XTAL2 f XTO ...
Page 28
... In a multichannel sys- tem, the CLK signal can either be not used or carefully laid out on the application PCB. The supply voltage of the microcontroller must also be carefully blocked in a multichannel system. ATA5423/ATA5425/ATA5428/ATA5429 28 f (MHz) ...
Page 29
... TX bit rate The clock cycle of the bit check and the TX bit rate depends on the selected bit-rate range (BR_Range) which is defined in control register 6 (see is defined in control register 4 (see the following formulas for further reference: BR_Range 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 f XTO ---------- - 3 = 2.38V (typically ...
Page 30
... EN VSOUT_EN (Control register 3) The supply voltage range of the ATA5423/ATA5425/ATA5428/ATA5429 is 2.4V to 3.6V or 4.4V to 6.6V. Pin VS1 is the supply voltage input for the range 2.4V to 3.6V and is used battery applica- tions (3V) using a single lithium 3V cell. Pin VS2 is the voltage input for the range 4. battery application (6V) and Base-station Application (5V) ...
Page 31
... VCC only temporarily. Otherwise, an additional current flows because pull-up resistor. There are two voltage monitors generating the following signals (see • DVCC_OK if DVCC > 1.5V typically • VSOUT_OK if VSOUT > V • Low_Batt if VSOUT < V 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 and Figure 2-3 on page 9). Figure 2.2 on page 8 and ...
Page 32
... V < 3.5V (typically), then the transceiver is in OFF mode. In OFF mode AVCC, DVCC and VAUX VSOUT are disabled, resulting in very low power consumption (I mode the transceiver is not programmable via the 4-wire serial interface. ATA5423/ATA5425/ATA5428/ATA5429 32 OFF Mode AVCC = OFF DVCC = OFF VSOUT = OFF ...
Page 33
... XTO has elapsed (amplitude detector, see Figure 4-2 on page time of the XTO has elapsed, the output clock at pin CLK is available. Because the enabling of pin CLK is asynchronous, the first clock cycle may be incomplete. 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 < VS1 + 0.5V, VSOUT is connected to VS1 Control Register 1 OPM1 0 Figure 5-3 on page 34 27) ...
Page 34
... DVCC_RESET N_RESET LOW_Batt (Status Register) VSOUT_EN (Control Register 3) VSOUT ATA5423/ATA5425/ATA5428/ATA5429 34 drops below V (typically 2.3V), N_RESET is set to low. If bit VSOUT_EN in con- Thres_1 If VSOUT < V (typically 2.3 V) the output of the pin CLK is low, the Microcontroller_Interface Thres_1 is disabled and the transceiver is not programmable via the 4-wire serial interface. ...
Page 35
... Figure 5-5. 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 Reset Logic, SR Latch Generates the Hysteresis in the NRESET Signal DVCC_OK and XTO_OK VSOUT_EN and VSOUT_OK LOW_BATT 1 Li Battery Application (3V) ATA5423/ATA5425/ VS1 ATA5428/ATA5429 VS2 VAUX RF Transceiver AVCC Digital Control DVCC Logic VSOUT VSINT CS SCK SDI_TMDI SDO_TMDO ...
Page 36
... The RAM and the status information are stored as long as the transceiver is in any active mode (DVCC = VS1 or DVCC = V_REG2) and are lost when the transceiver switches to OFF mode (DVCC =OFF). ATA5423/ATA5425/ATA5428/ATA5429 Battery Application (6V) with Inductive Emergency Supply ATA5423/ATA5425/ VS1 ATA5428/ATA5429 VS2 VAUX RF Transceiver AVCC Digital Control DVCC Logic ...
Page 37
... After the transceiver is turned on via pin PWR_ON = High Low Low Low Low Low or the voltage at pin VAUX V are in the default state. Figure 7-1. 7.2 TX/RX Data Buffer The TX/RX data buffer is used to handle the data transfer during RX and TX operations. 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 Register Structure MSB AVCC - IR1 IR0 FS ...
Page 38
... Table 7-4. FS Table 7-5. OPM1 ATA5423/ATA5425/ATA5428/ATA5429 38 Control Register 1 (Function of Bit 7 and Bit Mode) IR0 Function (RX Mode) Pin IRQ is set to “1” received bytes are in the TX/RX data buffer or a receiving error 0 occurred Pin IRQ is set to “1” received bytes are in the TX/RX data buffer or a receiving error ...
Page 39
... Note: Table 7-8. P_MODE Table 7-9. P_MODE 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 Control Register 1 (Function of Bit 0) Function 0 TX and RX function via TX/RX data buffer (default) Transparent mode, TX/RX data buffer disabled, TX modulation data stream via pin 1 SDI_TMDI, RX modulation data stream via pin SDO_TMDO ...
Page 40
... Control Register 3 (ADR 2) Table 7-10. FR12 Note: Table 7-11. VSOUT_EN Note: Table 7-12. CLK_ON Note: 7.3.4 Control Register 4 (ADR 3) Table 7-13. ASK_NFSK ATA5423/ATA5425/ATA5428/ATA5429 40 Control Register 3 (Function of Bit 7, Bit 6, Bit 5, Bit 4, Bit 3 and Bit 2) FR11 FR10 FR9 FR8 Tuning of f MSBs ...
Page 41
... Table 7-14. Sleep4 Table 7-15. XSleep Table 7-16. XLim 7.3.5 Control Register 5 (ADR 4) Table 7-17. BitChk1 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 Control Register 4 (Function of Bit 6, Bit 5, Bit 4, Bit 3 and Bit 2) Sleep3 Sleep2 Sleep1 Sleep0 Control Register 4 (Function of Bit 1) Function extended T off (default) ...
Page 42
... Table 7-19. Control Register 5 (Function of Bit 5, Bit 4, Bit 3, Bit 2, Bit 1 and Bit Mode) Lim_min5 Lim_min4 Lim_min3 7.3.6 Control Register 6 (ADR 5) Table 7-20. Baud1 ATA5423/ATA5425/ATA5428/ATA5429 42 Lim_min2 Lim_min1 Lim_min0 Lim_min2 Lim_min1 Lim_min0 Control Register 6 (Function of Bit 7 and Bit 6) Baud0 Function - Bit rate range 0 (B0) 1.0 Kbit/s to 2.5 Kbit/s; ...
Page 43
... Setting Power_On or P_On_Aux or an event on ST1, ST2, ST3, ST4 or ST5 is indicated by an IRQ. Reading the status register resets the bits Power_On, Low_Batt, P_On_Aux and the IRQ. 7.4.1 Status Register (ADR 8) Table 7-22. Status Bit ST5 ST4 ST3 ST2 ST1 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 Lim_max2 Lim_max1 Lim_max0 ...
Page 44
... CLK is available. Because the enabling of pin CLK is asynchro- nous, the first clock cycle may be incomplete. N_RESET is set to high if V (typically) and the XTO is settled. Figure 7-2. (Status register) ATA5423/ATA5425/ATA5428/ATA5429 44 Status Register (Continued) Function Indicates that the transceiver was woken up by pin PWR_ON (rising edge on pin PWR_ON). During Power_On = 1, the bits VSOUT_EN and CLK_ON in control register 3 are set to “ ...
Page 45
... The interrupt is deleted after reading the status register or executing the command Delete_IRQ. If pin Tn is not used, it can be left open because of an internal pull-up resistor (typically Figure 7-3. 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 T . DCLK Timing Flow Pin Tn, Status Bit STn ...
Page 46
... DVCC, AVCC N_RESET CLK Power_ON (Status register) IRQ OFF Mode ATA5423/ATA5425/ATA5428/ATA5429 46 ) for at least T (see Figure VS2 PWR_ON exceeds 1.5V (typically) and the XTO is settled, the digital control logic is active and PWR_ON_IRQ_2 It is not possible to set the transceiver to OFF mode by setting pin PWR_ON to “0”. If pin PWR_ON is not used, it must be connected to GND ...
Page 47
... If the transceiver is in any active mode (IDLE, TX, RX, RX_Polling), a positive edge on pin VAUX and V VAUX an interrupt. If P_On_Aux is still “1” during the positive edge on pin VAUX no interrupt is issued. P_On_Aux and the interrupt are deleted after reading the status register. 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 exceeds V VSOUT Figure 5-3 on page 34). Timing Status Bit Low_Batt ...
Page 48
... VAUX 2.0V (typ) V Thres_2 V VSOUT Thres_1 DVCC N_RESET CLK P_ON_AUX (Status register) IRQ OFF Mode ATA5423/ATA5425/ATA5428/ATA5429 48 V VAUX = 2.38V (typ) = 2.3V (typ) AUX Mode > VS1 + 0.5V (typ) V > VS1 + 0.5V (typ) VAUX IDLE, TX, RX, RX polling Mode 4841D–WIRE–10/07 ...
Page 49
... The control and status registers can be read individually or successively. Figure 8-3. Read Control/Status Register MSB SDI_TMDI Command: Read C/S Register X SDO_TMDO No. Bytes in the TX/RX Data Buffer SCK CS 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 LSB MSB LSB MSB X RX Data Byte 1 LSB MSB LSB MSB ...
Page 50
... The three most significant bits of the command (bit 5 to bit 7) indicate the command type. Bit 0 to bit 4 describe the target address when reading or writing a control or status register. In all other commands bit 0 to bit 4 have no effect and should be set to “0” for compatibility with future products. ATA5423/ATA5425/ATA5428/ATA5429 50 LSB MSB ...
Page 51
... When CS is low and the transparent mode is active (T_MODE = 1), the RX data stream is available on pin SDO_TMDO. Figure 8-7. Serial Timing SCK_setup1 SCK X T SDI_TMDI X T SDO_TMDO X can be either V 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 Command Structure MSB Bit 7 Bit the output level on pin N_RESET is low, no data communication with the microcontroller is possible. T CS_setup ...
Page 52
... T Bit-check on pin RX_ACTIVE (see rent consumption in RX polling mode I application (6V) or Base-station Application (5V). To calculate I by VS1,VS2 battery application (3V), VS2 battery application (6V) or VS2,VAUX in Base-station Application (5V) (see section I IDLE_X I = -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - P ATA5423/ATA5425/ATA5428/ATA5429 52 Control Register 1 OPM1 OPM0 During the start-up period IDLE_X ...
Page 53
... In US and European applications, the maximum value of T (which is done by setting the bit X 1 that case. The sleep time can be extended to about 300 ms by setting X (which is done by setting X 9.6 ms. 9.1.3 Start-up Mode During T circuit starts up (T ready to receive. 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 VSINT EXT , T and T ...
Page 54
... The incomming data stream is passed via the TX/RX Data Buffer to the connected microcontroller bit error occurs the transceiver is set back to Start-up mode. Output level on pin RX_ACTIVE High RX_X RX data stream is written into the TX/RX YES ATA5423/ATA5425/ATA5428/ATA5429 IDLE_X High Startup_PLL_X Startup_PLL High ...
Page 55
... The incomming data stream is passed via PIN SDO_TMDO to the connected microcontroller bit error occurs the transceiver is not set back to Start-up mode. Output level on pin RX_ACTIVE High RX_X RX data stream available on pin 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 = I S IDLE_X High Startup_PLL_X Startup_PLL High ...
Page 56
... T Startup_Sig_Proc Start-up mode As seen in the edge-to-edge time t limit T Lim_max the bit check will be terminated and the transceiver switches to sleep mode. Figure 9-4. ATA5423/ATA5425/ATA5428/ATA5429 56 shows an example where 3 bits are tested successfully. Bit check ok 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit T Bit-check ...
Page 57
... Figure 9-5. Timing Diagram During Bit Check (Lim_min = 14, Lim_max = 24) RX_ACTIVE Bit check Demod_Out Bit-check counter 0 T Startup_Sig_Proc Start-up mode 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 6. Using preburst patterns that contain various edge-to-edge time periods, Bit-check T = Lim_min Lim_min T = (Lim_max -1) Lim_max , T and T . The time resolution defining T ...
Page 58
... If no transmitter is present during the bit check, the output of the ASK/FSK demodulator delivers random signals. The bit check is a statistical process and T fore, an average value for T the selected bit-rate range and Bit-check ATA5423/ATA5425/ATA5428/ATA5429 58 Bit check failed (CV_Lim < Lim_min) 1/2 Bit 101112 T ...
Page 59
... Lim_min_2T Upper limit of 2T: Lim_max_2T T Lim_max_2T If the result of Lim_min_2T or Lim_max_2T is not an integer value, it will be rounded up. 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 , and the count of the bits, N Bit-check , requiring a higher value for the transmitter pre-burst, T Bit-check '0' '1' '0' '0' '0' '0' '0' '1' '1' '1' '1' '0' '0' '1' '1' '0' '1' '0' '1' '1' '0' '0' ...
Page 60
... If the bits OPM0 and OPM1 are still “1” after writing to a control register, the transceiver changes to the start-up mode (start-up signal processing). ATA5423/ATA5425/ATA5428/ATA5429 60 49). There is a counter that indicates the number of received bytes in the TX/RX “ ...
Page 61
... Lim_max = 38 (679 µs) 433.92 Lim_min = 13 (251 µs) (13.25311) Lim_max = 38 (715 µs) 868.3 Lim_min = 13 (248 µs) (13.41191) Lim_max = 38 (706 µs) 915 Lim_min = 13 (235 µs) (14.13324) Lim_max = 38 (670 µs) 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 Start-up mode Bit-check mode RX Modulation Scheme ASK/_NFSK T_MODE have been done with the Lim_min and Lim_max values according to 2 ...
Page 62
... IRQ is issued if the counter (while counting down) reaches the value defined by the control bits IR0 and IR1 in control register 1. Note: If T_Mode in control register 1 is set to “1”, the transceiver transparent mode. In this mode the TX/RX data buffer is disabled and the TX data stream must be applied on pin SDI_TMDI. ATA5423/ATA5425/ATA5428/ATA5429 62 Control Register 1 OPM1 0 Figure 9-11 on page “ ...
Page 63
... Figure 9-11. TX Operation (T_MODE = 0) Command: Delete_IRQ N Pin IRQ = Write Control Register 1 OPM1, OPM0: Set IDLE 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 Write Control Register 6 Baud1, BAUD0: Select baud rate range Lim_max0 to Lim_max5: Don't care Write Control Register 5 Lim_min0 to Lim_min5: Select the baud rate ...
Page 64
... Figure 9-12. TX Transparent Mode (T_MODE = 1) ATA5423/ATA5425/ATA5428/ATA5429 64 Write Control Register 4 XLim: Don't care ASK/_NFSK: Select modulation Sleep0 to Sleep4: Don't care XSleep: Don't care Write Control Register 3 FR7, FR8: Adjust f RF VSOUT_EN: Set VSOUT_EN = 1 CLK_ON: Don't care Write Control Register 2 FR0 to FR6: Adjust f ...
Page 65
... IR0 and IR1 in control register 1). Events During RX Operation (T_MODE = received bytes are in the RX data buffer or a receiving error is occurred (depends on IR0 and IR1 in control register 1). Successful bit check (P_MODE = 0) Note: 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 Bit in TX/RX P_Mode T_Mode Data Buffer ...
Page 66
... ESD (Human Body Model ESD S 5.1) every pin ESD (Machine Model JEDEC A115A) every pin ESD (Field Induced Charge Device Model ESD – STM 5.3.1 1999) every pin Maximum input level, input matched to 50 11. Thermal Resistance Parameters Junction ambient ATA5423/ATA5425/ATA5428/ATA5429 66 Symbol Min – stg – amb – ...
Page 67
... Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to with component values according to 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 = 25° 3.0V (1 amb VS1 VS2 (1) Pin ...
Page 68
... Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to with component values according to ATA5423/ATA5425/ATA5428/ATA5429 68 = 25° 3.0V (1 amb VS1 VS2 ...
Page 69
... Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to with component values according to 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 = 25° 3.0V (1 amb VS1 VS2 (1) Pin ...
Page 70
... Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to with component values according to ATA5423/ATA5425/ATA5428/ATA5429 70 = 25° 3.0V (1 amb VS1 VS2 (1) Pin ...
Page 71
... Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to with component values according to 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 = 25° 3.0V (1 amb VS1 VS2 ...
Page 72
... TX mode *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to with component values according to ATA5423/ATA5425/ATA5428/ATA5429 72 = 25° 3.0V (1 amb VS1 VS2 ...
Page 73
... Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to with component values according to 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 = 25° 3.0V (1 amb VS1 VS2 ...
Page 74
... Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to with component values according to ATA5423/ATA5425/ATA5428/ATA5429 74 = 25° 3.0V (1 amb VS1 VS2 (1) Pin Symbol = 868.3 MHz ...
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... RF *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to with component values according to 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 = 25° 3.0V (1 amb VS1 VS2 (1) Pin ...
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... V VS1 V VS1 *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to with component values according to ATA5423/ATA5425/ATA5428/ATA5429 76 = 25° 3.0V (1 amb VS1 VS2 (1) Pin ...
Page 77
... Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to with component values according to 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 = 25° 3.0V (1 amb VS1 VS2 (1) Pin ...
Page 78
... Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to with component values according to ATA5423/ATA5425/ATA5428/ATA5429 78 = 25° 3.0V (1 amb VS1 VS2 (1) Pin ...
Page 79
... TX mode) *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to with component values according to 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 = 25° 3.0V (1 amb VS1 VS2 ...
Page 80
... TX mode Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to with component values according to ATA5423/ATA5425/ATA5428/ATA5429 80 = 25° 3.0V (1 amb VS1 VS2 (1) Pin Symbol ...
Page 81
... RF *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to with component values according to 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 = 25° 3.0V (1 amb VS1 VS2 (1) Pin ...
Page 82
... Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to with component values according to ATA5423/ATA5425/ATA5428/ATA5429 82 = 25° 3.0V (1 amb VS1 VS2 ...
Page 83
... Figure 5-1 on page *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to with component values according to 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 = 25° 3.0V (1 amb VS1 VS2 ...
Page 84
... Supported voltage range 8.6 VAUX *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to with component values according to ATA5423/ATA5425/ATA5428/ATA5429 84 = 25° 3.0V (1 amb VS1 VS2 ...
Page 85
... V VS1 9.8 OFF mode V VSINT *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. The voltage of VAUX may rise up to 2V. The current I 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 = 25° 3.0V. Application according to amb VS1 VS2 Pin Symbol attery application 17, 18 ...
Page 86
... CLK enabled V Supply current VSOUT 9.17 TX mode CLK disabled V VSOUT *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. The voltage of VAUX may rise up to 2V. The current I ATA5423/ATA5425/ATA5428/ATA5429 86 = 25° 3.0V. Application according to amb VS1 VS2 Pin Symbol = V 3V ...
Page 87
... VS2 Supply current CLK enabled 10.11 RX mode V *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. The voltage of VAUX may rise The current I 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 = 25° 6.0V. Application according to amb VS2 Pin Symbol 17 4.4V VS2 ...
Page 88
... MHz/10 dBm CLK enabled V Supply current 10.16 TX mode CLK disabled V *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. The voltage of VAUX may rise The current I ATA5423/ATA5425/ATA5428/ATA5429 88 = 25° 6.0V. Application according to amb VS2 Pin Symbol = Startup_PLL_VS2 ...
Page 89
... Supply current in RX CLK enabled V 11.10 mode enabled Current during 11. pin VS2 I Startup_PLL VSOUT and VAUX *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 = 25° 5.0V. Application according to amb VS2 Pin Symbol - station 17, V VS2 19 station ...
Page 90
... MHz/10dBm 868.3 MHz/10dBm 868.3 MHz/10dBm 915 MHz/5dBm 915 MHz/10dBm CLK enabled V Supply current in 11.15 TX mode CLK disabled V *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA5423/ATA5425/ATA5428/ATA5429 90 = 25° 5.0V. Application according to amb VS2 Pin Symbol Startup_PLL_VS2,VAUX Startup_PLL ...
Page 91
... Bit-check N Bit-check N Bit-check BR_Range = BR_Range0 - 13.5 Bit rate range BR_Range1 BR_Range2 BR_Range3 *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 = 25° 3. battery application (3V)), V amb VS1 S2 - station Application(5V)) unless otherwise specified. Pin Symbol Startup_PLL ...
Page 92
... Time period SCK low to 15.9 CS high Time period SCK low to 15.10 CS low Time period CS low to 15.11 SCK high *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA5423/ATA5425/ATA5428/ATA5429 92 = 25° 3. battery application (3V)), V amb VS1 S2 - station Application(5V)) unless otherwise specified. ...
Page 93
... Base-station Application (5V Type means 100% tested 100% correlation tested Characterized on samples Design parameter 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 = 25° 3. battery application (3V)), V amb VS1 S2 - station Application(5V)) unless otherwise specified. Pin Symbol Figure 2-1 7, Figure 2.2 on and Figure 2-3 < (typ. 5 fF) < 2.2 pF (typ. 1.8 pF) 120 (typ ...
Page 94
... Base-station Application (5V Push button debounce Every mode except OFF 16.4 time mode *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA5423/ATA5425/ATA5428/ATA5429 94 = 25° 3. battery application (3V)), V amb VS1 S2 - station Application(5V)) unless otherwise specified. Pin Symbol 29 PWR_ON_IRQ_2 Figure 2-1 7, Figure 2 ...
Page 95
... Input current high *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note logic high level is applied to this pin, a minimum serial impedance of 100 must be ensured for proper operation over full temperature range. 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 – = 40°C to +85 ° amb VS1 = 4 ...
Page 96
... Saturation voltage low I DEM_OUT *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note logic high level is applied to this pin, a minimum serial impedance of 100 must be ensured for proper operation over full temperature range. ATA5423/ATA5425/ATA5428/ATA5429 96 – = 40°C to +85 ° amb VS1 = 4 ...
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... ATA5429 PLSW Note RoHS compliant 19. Package Information Package: QFN Exposed pad 5.1 x 5.1 Dimensions in mm Not indicated tolerances ± 0. Drawing-No.: 6.543-5089.02-4 Issue: 1; 14.01.03 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 Package Remarks QFN48 7 mm QFN48 7 mm QFN48 7 mm QFN48 7 mm QFN48 7 mm QFN48 7 mm ...
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... Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4841D-WIRE-10/07 4841C-WIRE-05/06 ATA5423/ATA5425/ATA5428/ATA5429 98 History Put datasheet in a new template Put datasheet in a new template kBaud replaced through Kbit/s Baud replaced through bit Table 9-6 “ ...
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... Thermal Resistance ............................................................................... 66 12 Electrical Characteristics: General ...................................................... 67 13 Electrical Characteristics Battery Application (3V) .................... 85 14 Electrical Characteristics Battery Application (6V) .................... 87 15 Electrical Characteristics: Base-station Application (5V) .................. 89 16 Digital Timing Characteristics .............................................................. 91 17 Digital Port Characteristics ................................................................... 95 18 Ordering Information ............................................................................. 97 19 Package Information ............................................................................. 97 20 Revision History ..................................................................................... 98 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 99 ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...