SI4021-A1-FT Silicon Laboratories Inc, SI4021-A1-FT Datasheet - Page 25

• Manufacturer Part Number: SI4021-A1-FT
• Description: IC TX FSK 915MHZ 5.4V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4021-A1-FT

• Package / Case: 16-TSSOP
• Frequency: 433MHz, 868MHz, 915MHz
• Modulation Or Protocol: FSK, OOK
• Data Rate - Maximum: 512kbps
• Power - Output: 8dBm
• Current - Transmitting: 24mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.2 V ~ 5.4 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 433 MHz to 915 MHz
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.2 V to 5.4 V
• Supply Current: 1.5 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Applications: -
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1622-5

RESET MODES
The chip will enter into reset mode if any of the following conditions are met:
Power-on reset
After power up the supply voltage starts to rise from 0V. The reset block has an internal ramping voltage reference (reset-ramp signal), which
is rising at 100mV/ms (typical) rate. The chip remains in reset state while the voltage difference between the actual V
reset-ramp signal is higher than the reset threshold voltage, which is 600 mV (typical). As long as the V
the chip stays in reset mode regardless the voltage difference between the V
The reset event can last up to 150ms supposing that the V
accept control commands via the serial control interface.
Power-on reset example:
Power glitch reset
The internal reset block has two basic mode of operation: normal and sensitive reset. The default mode is sensitive, which can be changed
by the appropriate control command (see Related control commands at the end of this section). In normal mode the power glitch detection
circuit is disabled.
There can be spikes or glitches on the V
high. In such cases if the sensitive reset is enabled an (unwanted) reset will be generated if the positive going edge of the V
rate greater than 100mV/ms and the voltage difference between the internal ramp signal and the V
(600 mV). Typical case when the battery is weak and due to its increased internal resistance a sudden decrease of the current consumption
(for example turning off the power amplifier) might lead to an increase in supply voltage. If for some reason the sensitive reset cannot be
disabled step-by-step decrease of the current consumption (by turning off the different stages one by one) can help to avoid this problem.
Any negative change in the supply voltage will not cause reset event unless the V
normal mode, 1.6V in sensitive reset mode).
If the sensitive mode is disabled and the power supply turned off the V
when the supply voltage is turned back on. If the decoupling capacitors keep their charges for a long time it could happen that no reset will
be generated upon power-up because the power glitch detector circuit is disabled.
Note that the reset event reinitializes the internal registers, so the sensitive mode will be enabled again.
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Power-on reset: During a power up sequence until the V
Power glitch reset: Transients present on the V
Software reset: Special control command received by the chip
dd
line if the supply filtering is not satisfactory or the internal resistance of the power supply is too
dd
line
dd
reaches 90% its final value within 1ms. During this period the chip does not
dd
has reached the correct level and stabilized
dd
must drop below 250mV in order to trigger a power-on reset event
dd
and the internal ramp signal.
dd
level reaches the reset threshold voltage (250mV in
dd
dd
reaches the reset threshold voltage
voltage is less than 1.6V (typical)
dd
and the internal
dd
has a rising
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