ATA8742-PXQW Atmel, ATA8742-PXQW Datasheet - Page 167

• Manufacturer Part Number: ATA8742-PXQW
• Description: MCU W/TRANSMITTER ASK/FSK 24QFN
• Manufacturer: Atmel

Specifications of ATA8742-PXQW

• Frequency: 433MHz
• Applications: Home Automation, Remote Sensing, RKE
• Modulation Or Protocol: ASK, FSK
• Data Rate - Maximum: 32 kBit/s
• Power - Output: 7.5dBm
• Current - Transmitting: 9.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 4kB Flash, 256B EEPROM, 256B SRAM
• Voltage - Supply: 2 V ~ 4 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Processor Series: ATA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 4 KB
• Data Ram Size: 256 B
• Interface Type: SPI, USI
• Maximum Clock Frequency: 8.1 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ATASTK512-EK1-IND
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

9151A–INDCO–07/09
Table 25-4.
Notes:
See
well as selections of offset calibration channels. MUX0 bit works as a gain selection bit for differ-
ential channels shown in
selected and when it is set (‘1’) 20x gain is selected. For normal differential channel pairs MUX5
bit work as a polarity reversal bit. Togling of the MUX5 bit exchanges the positive and negative
channel other way a round.
For offset calibration purpose the offset of the certain differential channels can be measure by
selecting the same input for both negative and positive input. This calibration can be done for
ADC0, ADC3 and ADC7.
detailed level.
Table 25-5 on page 168
1. See
2.
3. For offset calibration only .See
Reserved for reversal differential channels
“Temperature Measurement” on page 165
Reserved for differential channels
Single Ended Input channel Selections.
Table 25-5 on page 168
Reserved for offset calibration
Single Ended Input
ADC0 (PA0)
ADC1 (PA1)
ADC2 (PA2)
ADC3 (PA3)
ADC4 (PA4)
ADC5 (PA5)
ADC6 (PA6)
ADC7 (PA7)
0V (AGND)
1.1V (I Ref)
Table 25-5 on page
ADC8
“ADC Operation” on page 155
for details of selections of differential input channel selections as
(2)
for details.
Table 25-5 on page 168
(3)
(1)
168. When MUX0 bit is cleared (‘0’) 1x gain is
(1)
describes offset calibration in a more
and
“ADC Operation” on page 155
001000 - 011111
100011 - 100111
101000 - 111111
MUX5..0
000000
000001
000010
000011
000100
000101
000110
000111
100000
100001
100010
ATA8742
167