RFPIC12F675F-I/SS Microchip Technology, RFPIC12F675F-I/SS Datasheet - Page 28

IC MCU 1KX14 RF FSK/ASK 20SSOP

RFPIC12F675F-I/SS

Manufacturer Part Number
RFPIC12F675F-I/SS
Description
IC MCU 1KX14 RF FSK/ASK 20SSOP
Manufacturer
Microchip Technology
Series
PIC®r
Datasheets

Specifications of RFPIC12F675F-I/SS

Package / Case
20-SSOP
Frequency
380MHz ~ 450MHz
Applications
RKE, Security Systems
Modulation Or Protocol
ASK, FSK
Data Rate - Maximum
40 kbps
Power - Output
10dBm
Current - Transmitting
14mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Memory Size
1024 x 14 words Flash, 128 x 8 Byte EEPROM, 64 x 8 Byte SRAM
Voltage - Supply
2V ~ 5.5V
Operating Temperature
-40°C ~ 125°C
Processor Series
RFPIC12F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ICE2000, DV164102, AC164101, AC164103
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
Program Memory Type
Flash
Program Memory Size
1.75 KB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164103 - MODULE RCVR RFPIC 433MHZAC164101 - MODULE TRANSMITTER RFPIC 433MHZDV164102 - KIT DEV RFPICKIT KIT 1AC124002 - MOD SKT PROMATEII 18SOIC/20SSOP
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q3188156

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rfPIC12F675
4.3
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI, with the internal phase clocks, is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2T
REGISTER 4-1:
DS70091A-page 26
Using Timer0 with an External
Clock
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
OPTION_REG — OPTION REGISTER (ADDRESS: 81h)
bit 7
GPPU: GPIO Pull-up Enable bit
1 = GPIO pull-ups are disabled
0 = GPIO pull-ups are enabled by individual port latch values
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of GP2/INT pin
0 = Interrupt on falling edge of GP2/INT pin
T0CS: TMR0 Clock Source Select bit
1 = Transition on GP2/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on GP2/T0CKI pin
0 = Increment on low-to-high transition on GP2/T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the TIMER0 module
PS2:PS0: Prescaler Rate Select bits
Legend:
R = Readable bit
- n = Value at POR
GPPU
R/W-1
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
INTEDG
R/W-1
OSC
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
R/W-1
T0CS
(and
Preliminary
W = Writable bit
’1’ = Bit is set
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
R/W-1
T0SE
a small RC delay of 20 ns) and low for at least 2T
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
Note:
R/W-1
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
PSA
The ANSEL (9Fh) and CMCON (19h)
registers must be initialized to configure an
analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
R/W-1
PS2
 2003 Microchip Technology Inc.
x = Bit is unknown
R/W-1
PS1
R/W-1
PS0
bit 0
OSC

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