RFPIC12F675F-I/SS Microchip Technology, RFPIC12F675F-I/SS Datasheet - Page 72

• Manufacturer Part Number: RFPIC12F675F-I/SS
• Description: IC MCU 1KX14 RF FSK/ASK 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC®r

Specifications of RFPIC12F675F-I/SS

• Package / Case: 20-SSOP
• Frequency: 380MHz ~ 450MHz
• Applications: RKE, Security Systems
• Modulation Or Protocol: ASK, FSK
• Data Rate - Maximum: 40 kbps
• Power - Output: 10dBm
• Current - Transmitting: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 1024 x 14 words Flash, 128 x 8 Byte EEPROM, 64 x 8 Byte SRAM
• Voltage - Supply: 2V ~ 5.5V
• Operating Temperature: -40°C ~ 125°C
• Processor Series: RFPIC12F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000, DV164102, AC164101, AC164103
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 1.75 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164103 - MODULE RCVR RFPIC 433MHZAC164101 - MODULE TRANSMITTER RFPIC 433MHZDV164102 - KIT DEV RFPICKIT KIT 1AC124002 - MOD SKT PROMATEII 18SOIC/20SSOP
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3188156

rfPIC12F675
10.9
The Power-down mode is entered by executing a
SLEEP
If the Watchdog Timer is enabled:
• WDT will be cleared but keeps running
• PD bit in the STATUS register is cleared
• TO bit is set
• Oscillator driver is turned off
• I/O ports maintain the status they had before
For lowest current consumption in this mode, all I/O
pins should be either at V
circuitry drawing current from the I/O pin and the
comparators and CV
that are hi-impedance inputs should be pulled high or
low externally to avoid switching currents caused by
floating inputs. The T0CKI input should also be at V
or V
tion from on-chip pull-ups on GPIO should be
considered.
The MCLR pin must be at a logic high level (V
10.9.1
The device can wake-up from SLEEP through one of
the following events:
FIGURE 10-13:
DS70091A-page 70
INSTRUCTION FLOW
(INTCON<1>)
SLEEP
hi-impedance).
Note:
(INTCON<7>)
Note
INTF flag
GIE bit
Instruction
Fetched
Instruction
Executed
CLKOUT
SS
INT pin
for lowest current consumption. The contribu-
instruction.
OSC1
1:
2:
3:
4:
Power-Down Mode (SLEEP)
PC
was executed (driving high, low, or
(4)
It should be noted that a RESET generated
by a WDT time-out does not drive MCLR
pin low.
WAKE-UP FROM SLEEP
XT, HS or LP Oscillator mode assumed.
T
SLEEP delay in INTOSC mode.
GIE = '1' assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
CLKOUT is not available in XT, HS, LP or EC Osc modes, but shown here for timing reference.
OST
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Inst(PC) = SLEEP
= 1024T
Inst(PC - 1)
PC
REF
WAKE-UP FROM SLEEP THROUGH INTERRUPT
OSC
should be disabled. I/O pins
DD
(drawing not to scale). Approximately 1 µs delay will be there for RC Osc mode. See Section 12 for wake-up from
, or V
Inst(PC + 1)
SLEEP
PC+1
SS
, with no external
Processor in
SLEEP
IHMC
PC+2
).
Preliminary
DD
T
OST
(2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Interrupt Latency
Inst(PC + 2)
Inst(PC + 1)
1.
2.
3.
The first event will cause a device RESET. The two
latter events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of device RESET.
The PD bit, which is set on power-up, is cleared when
SLEEP is invoked. TO bit is cleared if WDT Wake-up
occurred.
When the
next instruction (PC + 1) is pre-fetched. For the device
to wake-up through an interrupt event, the correspond-
ing interrupt enable bit must be set (enabled). Wake-up
is regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the
set (enabled), the device executes the instruction after
the
address (0004h). In cases where the execution of the
instruction following
should have an
The WDT is cleared when the device wakes up from
SLEEP, regardless of the source of wake-up.
(Note 2)
PC+2
Note:
SLEEP
External RESET input on MCLR pin
Watchdog Timer Wake-up (if WDT was enabled)
Interrupt from GP2/INT pin, GPIO change, or a
peripheral interrupt.
SLEEP
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will
immediately wake-up from SLEEP. The
SLEEP instruction is completely executed.
Dummy cycle
instruction, then branches to the interrupt
PC + 2
NOP
instruction is being executed, the
SLEEP
SLEEP
after the
 2003 Microchip Technology Inc.
Inst(0004h)
Dummy cycle
instruction. If the GIE bit is
0004h
is not desirable, the user
SLEEP
instruction.
Inst(0005h)
Inst(0004h)
0005h