XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 121
XRT94L33IB-L
Manufacturer Part Number
XRT94L33IB-L
Description
IC MAPPER DS3/E3/STS-1 504TBGA
Manufacturer
Exar Corporation
Specifications of XRT94L33IB-L
Applications
Network Switches
Interface
Bus
Voltage - Supply
3.14 V ~ 3.47 V
Package / Case
504-LBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Quantity
Price
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Part Number:
XRT94L33IB-L
Manufacturer:
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Quantity:
10 000
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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
• To optionally transmit the AIS-P indicator, in the down-stream direction (towards the Receive ATM Cell or
Receive PPP Packet Processor Blocks) anytime (and for the duration that) the Receive SONET POH
Processor declares the AIS-P, LOP-P, UNEQ-P, PLM-P or TIM-P defect conditions
• To declare and clear the LOP-C and AIS-C defect condition.
• To compute and verify the B3 byte of the incoming STS-3 SPE.
• To detect and increment Performance Monitor registers anytime it detects B3 byte errors in the incoming
STS-1 SPE data-stream.
• To detect and increment performance monitor registers anytime it detects any REI-P events.
• To receive and process Path Trace messages via the J1 byte.
• To route the STS-1 SPE data to the Receive ATM Cell Processor or Receive PPP Packet Processor blocks
for further processing.
1.2.5
The purpose of the “Receive ATM Cell Processor” block is to extract out the data (being carried by its
corresponding incoming STS-1 SPE data-stream) and to perform the following operations on it.
• Cell Delineation
• HEC Byte Verification
• Idle Cell Filtering
• User Cell Filtering
• To receive cells, with “user-specified” header bytes and to load them into the “Receive Cell Extraction
Memory Buffer” (where they can be read out and accessed by the Microprocessor Interface)
• To read out a “user-specified” ATM cell (which is residing in the Receive Cell Insertion Buffer) and to insert
this cell into the “Receive ATM Cell” traffic.
• To route all filtered cells to the “Receive ATM Cell Buffer” (where it will be made available to the ATM Layer
Processor via the Receive UTOPIA Interface block).
1.2.6
The purpose of the Receive UTOPIA Interface Block is to provide a standard UTOPIA Level 1, 2 or 3 interface
to the ATM Layer Processor; for reading out the contents of all ATM cells that are written into the “Receive
ATM Cell Buffer”.
The Receive UTOPIA Interface block can be configured to operate with either an 8 or 16-bit wide “Receive
UTOPIA Data” bus.
Note:
1.2.7
The purpose of the Transmit UTOPIA Interface Block is to provide a standard UTOPIA Level 1, 2 or 3
interface to the ATM Layer Processor, for writing in the contents of all “Valid” ATM cells, into the “Transmit
Cell Buffer”.
The Transmit UTOPIA Interface block can be configured to operate with either an 8 or 16-bit wide “Transmit
UTOPIA Data” bus.
Note:
The Receive UTOPIA Interface Block supports “UTOPIA Level 3” from a signaling stand-point. The Receive
The Transmit UTOPIA Interface Block supports “UTOPIA Level 3” from a signaling stand-point. The Receive
UTOPIA Interface Block within the XRT94L33 still only supports a 16-bit wide (not 32-bit wide) UTOPIA Bus and
only operates up to 50MHz (not 100MHz).
UTOPIA Interface Block within the XRT94L33 still only supports a 16-bit wide (not 32-bit wide) UTOPIA Bus and
only operates up to 50MHz (not 100MHz).
T
T
T
HE
HE
HE
R
R
T
RANSMIT
ECEIVE
ECEIVE
ATM C
UTOPIA I
UTOPIA I
ELL
NTERFACE
P
NTERFACE
ROCESSOR
B
B
LOCK
LOCK
B
LOCK
121
XRT94L33
Rev.1.2.0.
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