XC4VFX40-11FF1152I Xilinx Inc, XC4VFX40-11FF1152I Datasheet

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XC4VFX40-11FF1152I

Manufacturer Part Number
XC4VFX40-11FF1152I
Description
IC FPGA VIRTEX-4FX 1152FFBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Datasheet

Specifications of XC4VFX40-11FF1152I

Number Of Logic Elements/cells
41904
Number Of Labs/clbs
4656
Total Ram Bits
2654208
Number Of I /o
448
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1152-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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`
DS112 (v3.1) August 30, 2010
General Description
Combining Advanced Silicon Modular Block (ASMBL™) architecture with a wide variety of flexible features, the Virtex®-4
family from Xilinx greatly enhances programmable logic design capabilities, making it a powerful alternative to ASIC
technology. Virtex-4 FPGAs comprise three platform families—LX, FX, and SX—offering multiple feature choices and
combinations to address all complex applications. The wide array of Virtex-4 FPGA hard-IP core blocks includes the
PowerPC® processors (with a new APU interface), tri-mode Ethernet MACs, 622 Mb/s to 6.5 Gb/s serial transceivers,
dedicated DSP slices, high-speed clock management circuitry, and source-synchronous interface blocks. The basic Virtex-4
FPGA building blocks are enhancements of those found in the popular Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and
Virtex-II Pro X product families, so previous-generation designs are upward compatible. Virtex-4 devices are produced on a
state-of-the-art 90 nm copper process using 300 mm (12-inch) wafer technology.
Summary of Virtex-4 Family Features
Table 1: Virtex-4 FPGA Family Members
© Copyright 2004–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. All other trademarks are the property of their respective owners.
DS112 (v3.1) August 30, 2010
Product Specification
XC4VLX15
XC4VLX25
XC4VLX40
XC4VLX60
XC4VLX80
XC4VLX100
XC4VLX160
XC4VLX200 192 x 116 200,448 89,088
Device
Three Families — LX/SX/FX
-
-
-
Xesium™ Clock Technology
-
-
-
XtremeDSP™ Slice
-
-
-
Smart RAM Memory Hierarchy
-
-
-
Virtex-4 LX: High-performance logic applications solution
Virtex-4 SX: High-performance solution for digital signal
processing (DSP) applications
Virtex-4 FX: High-performance, full-featured solution for
embedded platform applications
Digital clock manager (DCM) blocks
Additional phase-matched clock dividers (PMCD)
Differential global clocks
18 x 18, two’s complement, signed Multiplier
Optional pipeline stages
Built-in Accumulator (48-bit) and Adder/Subtracter
Distributed RAM
Dual-port 18-Kbit RAM blocks
·
·
High-speed memory interface supports DDR and DDR-2
SDRAM, QDR-II, and RLDRAM-II.
Optional pipeline stages
Optional programmable FIFO logic automatically
remaps RAM signals as FIFO signals
Row x Col
128 x 36
128 x 52
160 x 56
192 x 64
192 x 88
64 x 24
96 x 28
Array
Configurable Logic Blocks (CLBs)
(3)
110,592 49,152
152,064 67,584
13,824
24,192
41,472
59,904
80,640
Logic
Cells
R
10,752
18,432
26,624
35,840
Slices
6,144
Distributed
RAM (Kb)
1056
1392
Max
168
288
416
560
768
96
(1)
XtremeDSP
Slices
32
48
64
64
80
96
96
96
0
0
(2)
www.xilinx.com
Blocks
18 Kb
160
200
240
288
336
48
72
96
0
Block RAM
RAM (Kb)
Virtex-4 Family Overview
Product Specification
1,296
1,728
2,880
3,600
4,320
5,184
6,048
Block
Max
864
SelectIO™ Technology
-
-
-
-
Flexible Logic Resources
Secure Chip AES Bitstream Encryption
90 nm Copper CMOS Process
1.2V Core Voltage
Flip-Chip Packaging including Pb-Free Package
Choices
RocketIO™ 622 Mb/s to 6.5 Gb/s Multi-Gigabit
Transceiver (MGT) [FX only]
IBM PowerPC RISC Processor Core [FX only]
-
-
Multiple Tri-Mode Ethernet MACs [FX only]
DCMs PMCDs
1.5V to 3.3V I/O operation
Built-in ChipSync™ source-synchronous technology
Digitally controlled impedance (DCI) active termination
Fine grained I/O banking (configuration in one bank)
PowerPC 405 (PPC405) Core
Auxiliary Processor Unit Interface (User Coprocessor)
12
12
12
12
4
8
8
8
0
4
4
4
8
8
8
8
Processor
PowerPC
Blocks
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Ethernet
MACs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Transceiver
RocketIO
Blocks
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Banks
Total
I/O
11
13
13
15
17
17
17
9
User
Max
320
448
640
640
768
960
960
960
I/O
1

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XC4VFX40-11FF1152I Summary of contents

Page 1

R DS112 (v3.1) August 30, 2010 General Description Combining Advanced Silicon Modular Block (ASMBL™) architecture with a wide variety of flexible features, the Virtex®-4 family from Xilinx greatly enhances programmable logic design capabilities, making it a powerful alternative to ...

Page 2

... XC4VSX35 34,560 15,360 XC4VSX55 128 x 48 55,296 24,576 XC4VFX12 12,312 5,472 XC4VFX20 19,224 8,544 XC4VFX40 41,904 18,624 XC4VFX60 128 x 52 56,880 25,280 XC4VFX100 160 x 68 94,896 42,176 XC4VFX140 192 x 84 142,128 63,168 Notes: 1. One CLB = Four Slices = Maximum of 64 bits. ...

Page 3

R SelectIO Technology • 960 user I/Os • Wide selections of I/O standards from 1.5V to 3.3V • Extremely high-performance - 600 Mb/s HSTL & SSTL (on all single-ended I/ Gb/s LVDS (on all differential I/O ...

Page 4

R Architectural Description: Virtex-4 FPGA Array Overview Virtex-4 devices are user-programmable gate arrays with various configurable elements and embedded cores opti- mized for high-density and high-performance system designs. Virtex-4 devices implement the following function- ality: • I/O blocks provide the ...

Page 5

R range of signal delays. This is especially useful for synchro- nizing signal edges in source synchronous interfaces. General purpose I/O in select locations (four per bank) are designed to be “regional clock capable” I/O by adding spe- cial hardware ...

Page 6

R Virtex-4 FX Family This section briefly describes blocks available only in FX devices. RocketIO Multi-Gigabit Transceiver 8 – 24 Channels RocketIO Multi-Gigabit Serial Transceivers (MGTs) capable of running 622 Mb/s – 6.5 Gb/s • Full Clock and Data Recovery ...

Page 7

... N/A XC4VSX35 N/A XC4VSX55 XC4VFX12 N/A 240 N/A XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 Notes: 1. All packages are also available in Pb-Free versions (SFG/FFG). 2. Pinouts on all packages (except SF363/SFG363 and FF668/FFG668) are configured using the new, improved SparseChevron pin layout for superior signal integrity. ...

Page 8

... Revised the CLB numbers for XC4VFX40 devices in Added stepping to order information example in Changed maximum transceiver rate to 6.5 Gb/s. Removed FF1760 package from Table Table 1: Corrected typo: XC4VFX40 number of slices = 18,624. Table 2: Added column for FF676 package. Rewrote table footnotes. www.xilinx.com Virtex-4 Family Overview Revision Table 1 ...

Page 9

R Date Version 03/12/07 2.1 Table XC4VSX25, XC4VSX35, and XC4VFX12 devices. 09/28/07 3.0 All Virtex-4 devices released to Production status. See DS302, Virtex-4 Data Sheet, for full particulars. No changes in this document from previous revision. 08/30/10 3.1 See detailed ...

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