NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 10

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 5-80 Format of ACK FIELD............................................................................................... 426
Figure 5-81 Format of REMOTE FRAME .................................................................................... 427
Figure 5-82 Format of ERROR FRAME....................................................................................... 427
Figure 5-83 PS/2 Device Block Diagram ..................................................................................... 454
Figure 5-84 Data Format of Device-to-Host................................................................................. 456
Figure 5-85 Data Format of Host-to-Device................................................................................. 456
Figure 5-86 PS/2 Bit Data Format................................................................................................ 457
Figure 5-87 PS/2 Bus Timing ....................................................................................................... 457
Figure 5-88 PS/2 Data Format ..................................................................................................... 459
Figure 5-89 I
Figure 5-90 I
Figure 5-91 I
Figure 5-92 MSB Justified Timing Diagram (Format=1) .............................................................. 470
Figure 5-93 FIFO contents for various I
Figure 5-94 ADC Controller Block Diagram ................................................................................. 486
Figure 5-95 ADC Converter Self-Calibration Timing Diagram ..................................................... 487
Figure 5-96 ADC Clock Control.................................................................................................... 488
Figure 5-97 Single Mode Conversion Timing Diagram ................................................................ 488
Figure 5-98 Single-Cycle Scan on Enabled Channels Timing Diagram ...................................... 489
Figure 5-99 Continuous Scan on Enabled Channels Timing Diagram ........................................ 490
Figure 5-100 A/D Conversion Result Monitor Logics Diagram .................................................... 491
Figure 5-101 A/D Controller Interrupt........................................................................................... 492
Figure 5-102 ADC single-end input conversion voltage and conversion result mapping diagram
Figure 5-103 ADC differential input conversion voltage and conversion result mapping diagram
Figure 5-104 Analog Comparator Block Diagram ........................................................................ 509
Figure 5-105 Comparator Controller Interrupt Sources ............................................................... 510
Figure 5-106 Medium Density PDMA Controller Block Diagram ................................................. 516
Figure 5-107 Low Density PDMA Controller Block Diagram........................................................ 517
Figure 5-108 EBI Block Diagram................................................................................................. 542
Figure 5-109 Connection of 16-bit EBI Data Width with 16-bit Device ....................................... 543
Figure 5-110 Connection of 8-bit EBI Data Width with 8-bit Device ............................................ 543
Figure 5-111 Timing Control Waveform for 16bit Data Width..................................................... 545
Figure 5-112 Timing Control Waveform for 8bit Data Width....................................................... 546
Figure 5-113 Timing Control Waveform for Insert Idle Cycle....................................................... 547
Figure 6-1 Medium Density Flash Memory Control Block Diagram............................................. 552
Figure 6-2 Low Density Flash Memory Control Block Diagram ................................................... 553
..................................................................................................................................................... 496
..................................................................................................................................................... 496
NuMicro™ NUC100 Series Technical Reference Manual
2
2
2
S Clock Control Diagram........................................................................................ 469
S Controller Block Diagram .................................................................................... 469
S Bus Timing Diagram (Format =0) ....................................................................... 470
2
S modes ....................................................................... 471
- 10 -
Publication Release Date: Dec. 22, 2010
Revision V1.06