NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 124

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Peripheral Reset Control Register2 (IPRSTC2)
Setting these bits 1 will generate asynchronous reset signals to the corresponding IP controller.
Users need to set these bits to 0 to release corresponding IP controller from reset state
Register
IPRSTC2
Bits
[31:30]
[29]
[28]
[27]
[26:25]
[24]
[23]
[22]
[21]
SPI3_RST
PS2_RST
31
23
15
7
Reserved
Reserved
NuMicro™ NUC100 Series Technical Reference Manual
Descriptions
Reserved
I2S_RST
ADC_RST
USBD_RST
Reserved
CAN0_RST
PS2_RST
ACMP_RST
PWM47_RST
ACMP_RST PWM47_RST PWM03_RST
Offset
GCR_BA+0x0C
SPI2_RST
30
22
14
6
TMR3_RST
SPI1_RST
I2S_RST
Reserved
I
1 = I
0 = I
ADC Controller Reset
1 = ADC controller reset
0 = ADC controller normal operation
USB Device Controller Reset
1 = USB device controller reset
0 = USB device controller normal operation
Reserved
CAN0 Controller Reset
1 = CAN0 controller reset
0 = CAN0 controller normal operation
PS2 Controller Reset
1 = PS2 controller reset
0 = PS2 controller normal operation
Analog Comparator Controller Reset
1 = Analog Comparator controller reset
0 = Analog Comparator controller normal operation
PWM47 controller Reset (Medium Density Only)
R/W
R/W
2
S Controller Reset
29
21
13
5
2
2
S controller reset
S controller normal operation
Description
Peripheral Controller Reset Control Register 2
TMR2_RST
ADC_RST
SPI0_RST
28
20
12
4
- 124 -
USBD_RST
TMR1_RST
Reserved
27
19
11
3
Reserved
Publication Release Date: Dec. 22, 2010
UART2_RST UART1_RST UART0_RST
TMR0_RST
26
18
10
2
Reserved
GPIO_RST
I2C1_RST
25
17
9
1
Revision V1.06
Reset Value
0x0000_0000
CAN0_RST
I2C0_RST
Reserved
24
16
8
0