NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 265

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.6.4.3
5.6.4.4
The CPU can read from and write to this 8-bit field of I2CON [7:0] directly. Two bits are affected
by hardware: the SI bit is set when the I
cleared when a STOP condition is present on the bus. The STO bit is also cleared when ENS1 =
0.
EI
ENSI
STA
STO
SI
AA
I2CSTATUS [7:0] is an 8-bit read-only register. The three least significant bits are always 0. The
bit field I2CSTATUS [7:3] contain the status code. There are 26 possible status codes, All states
are listed in section 5.6.6. When I2CSTATUS [7:0] contains F8H, no serial interrupt is requested.
All other I2CSTATUS [7:3] values correspond to defined I
entered, a status interrupt is requested (SI = 1). A valid status code is present in I2CSTATUS[7:3]
one cycle after SI is set by hardware and is still present one cycle after SI has been reset by
software.
In addition, state 00H stands for a Bus Error. A Bus Error occurs when a START or STOP
condition is present at an illegal position in the format frame. Examples of illegal positions are
during the serial transfer of an address byte, a data byte or an acknowledge bit. To recover I
Control Register (I2CON)
Status Register (I2CSTATUS)
Enable Interrupt.
Set to enable I
The Multi Function pin function of SDA and SCL must be set to I
I
sends a START or repeat START condition to bus when the bus is free.
I
then I
be cleared by hardware automatically. In a slave mode, setting STO resets I
to the defined “not addressed” slave mode. This means it is NO LONGER in the slave
receiver mode to receive data from the master transmit device.
I
is set by hardware, and if bit EI (I2CON [7]) is set, the I
be cleared by software. Clear SI is by writing 1 to this bit. All states are listed in section
5.6.6
Assert Acknowledge Control Bit. When AA=1 prior to address or data received, an
acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on
the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The
receiver devices are acknowledging the data sent by transmitter. When AA=0 prior to
address or data received, a Not acknowledged (high level to SDA) will be returned during
the acknowledge clock pulse on the SCL line.
2
2
2
I2CDAT.7
I2C Data Register:
C START Control Bit. Setting STA to logic 1 to enter master mode, the I
C STOP Control Bit. In master mode, setting STO to transmit a STOP condition to bus
C Interrupt Flag. When a new I
NuMicro™ NUC100 Series Technical Reference Manual
2
C hardware will check the bus condition if a STOP condition is detected this flag will
I2CDAT.6 I2CDAT.5 I2CDAT.4 I2CDAT.3 I2CDAT.2 I2CDAT.1 I2CDAT.0
2
C serial function controller. When ENSI=1 the I
Figure 5-24 I
2
2
2
C hardware requests a serial interrupt, and the STO bit is
C Data Shifting Direction
C state is present in the I2CSTATUS register, the SI flag
shifting direction
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Publication Release Date: Oct 22, 2010
C states. When each of these states is
2
C interrupt is requested. SI must
2
2
C serial function enables.
C function.
Revision V1.06
2
2
C hardware
C hardware
2
C