NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 356

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.9.8
SPI Control and Status Register (SPI_CNTRL)
Register
SPI_CNTRL
Bits
[31:24]
[23]
[22]
[21]
[20:19]
VARCLK_EN
Register Description
31
23
15
7
NuMicro™ NUC100 Series Technical Reference Manual
Offset
SPIx_BA+0x00
Descriptions
Reserved
VARCLK_EN
TWOB
Reserved
REORDER
TWOB
30
22
14
6
SP_CYCLE
TX_BIT_LEN
Reserved
R/W
R/W
Reserved
Variable Clock Enable (Master Only)
1 = The serial clock output frequency is variable. The output frequency is decided by
0 = The serial clock output frequency is fixed and decided only by the value of
Note that when enable this VARCLK_EN bit, the setting of TX_BIT_LEN must be
programmed as 0x10 (16 bits mode)
Two Bits Transfer Mode Active
1 = Enable two-bit transfer mode.
0 = Disable two-bit transfer mode.
Note that when enable TWOB, the serial transmitted 2-bit data output are from
SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0.
Note that when enable TWOB, the setting of TX_NUM must be programmed as 0x00
Reserved
Reorder Mode Select
00 = Disable both byte reorder and byte suspend functions.
01 = Enable byte reorder function and insert a byte suspend interval (2~17 SPICLK
10 = Enable byte reorder function, but disable byte suspend function.
11 = Disable byte reorder function, but insert a suspend interval (2~17 SPICLK cycles)
29
21
13
5
the value of VARCLK, DIVIDER, and DIVIDER2.
DIVIDER.
cycles) among each byte. The setting of TX_BIT_LEN must be configured as
0x00. (32 bits/word)
among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32
bits/word)
Description
Control and Status Register
28
20
12
4
- 356 -
REORDER
Reserved
CLKP
27
19
11
3
Publication Release Date: Dec. 22, 2010
TX_NEG
SLAVE
LSB
26
18
10
2
RX_NEG
25
17
IE
9
1
TX_NUM
Revision V1.06
Reset Value
0x0500_0004
GO_BUSY
24
16
IF
8
0