NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 370

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.10.6 Register Description
Timer Control Register (TCSR)
Register
TCSR0
TCSR1
TCSR2
TCSR3
Bits
[31]
[30]
[29]
[28:27]
Reserved
31
23
15
7
NuMicro™ NUC100 Series Technical Reference Manual
Offset
TMR_BA01+0x00 R/W
TMR_BA01+0x20 R/W
TMR_BA23+0x00 R/W
TMR_BA23+0x20 R/W
Descriptions
Reserved
CEN
IE
MODE
CEN
30
22
14
6
R/W
Reserved
Timer Enable Bit
1 = Starts counting
0 = Stops/Suspends counting
Note1: In stop status, and then set CEN to 1 will enables the 24-bit up-timer keeps up
counting from the last stop counting value.
Note2: This bit is auto-cleared by hardware in one-shot mode (MODE [28:27] =00)
when the associated timer interrupt is generated (IE [29] =1).
Interrupt Enable Bit
1 = Enable timer Interrupt
0 = Disable timer Interrupt
If timer interrupt is enabled, the timer asserts its interrupt signal when the associated
up-timer value is equal to TCMPR.
Timer Operating Mode
29
21
13
MODE
00
IE
5
Description
Timer0 Control and Status Register
Timer1 Control and Status Register
Timer2 Control and Status Register
Timer3 Control and Status Register
Reserved
28
20
12
PRESCALE[7:0]
4
- 370 -
MODE[1:0]
Reserved
Timer Operating Mode
The timer is operating in the one-shot mode. The associated interrupt
signal is generated once (if IE is enabled) and CEN is automatically
27
19
11
3
Publication Release Date: Dec. 22, 2010
CRST
26
18
10
2
CACT
25
17
9
1
Revision V1.06
Reset Value
0x0000_0005
0x0000_0005
0x0000_0005
0x0000_0005
TDR_EN
CTB
24
16
8
0