NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 406

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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NuMicro™ NUC100 Series Technical Reference Manual
RX_FULL
RX_EMPTY
RX_POINTER
Reserved
BIF
FEF
PEF
RS485_ADD_DETF
Reserved
RX_OVER_IF
Transmitter Shift Register, TX_POINTER decreases one.
Receiver FIFO Full (Read Only)
This bit initiates RX FIFO full or not.
This bit is set when RX_POINTER is equal to 64/16(UART0/UART1), otherwise is
cleared by hardware.
Receiver FIFO Empty (Read Only)
This bit initiate RX FIFO empty or not.
When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It
will be cleared when UART receives any new data.
RX FIFO Pointer (Read Only)
This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from
external device, RX_POINTER increases one. When one byte of RX FIFO is read by
CPU, RX_POINTER decreases one.
Reserved
Break Interrupt Flag (Read Only)
This bit is set to a logic 1 whenever the received data input(RX) is held in the
“spacing state” (logic 0) for longer than a full word transmission time (that is, the total
time of “start bit” + data bits + parity + stop bits) and is reset whenever the CPU
writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing ‘1’ to it.
Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid “stop
bit” (that is, the stop bit following the last data bit or parity bit is detected as a logic 0),
and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing ‘1’ to it.
Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid “parity
bit”, and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing ‘1’ to it.
RS-485 Address Byte Detection Flag (Read Only) (Low Density Only)
This bit is set to logic 1 and set UA_ALT_CSR [RS-485_ADD_EN] whenever in RS-
485 mode the receiver detect any address byte received address byte character (bit9
= ‘1’) bit", and it is reset whenever the CPU writes 1 to this bit.
Note: This field is used for RS-485 function mode.
Note: This bit is read only, but can be cleared by writing ‘1’ to it.
Reserved
RX Overflow Error IF (Read Only)
This bit is set when RX FIFO overflow.
If the number of bytes of received data is greater than RX_FIFO (UA_RBR) size,
64/16 bytes of UART0/UART1, this bit will be set.
Note: This bit is read only, but can be cleared by writing ‘1’ to it.
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Publication Release Date: Dec. 22, 2010
Revision V1.06