NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 461

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.14.6 Register Description
PS2 Control Register (PS2CON)
Register
PS2CON
Bits
[31:12]
[11]
[10]
[9]
[8]
[7]
ACK
31
23
15
7
NuMicro™ NUC100 Series Technical Reference Manual
Offset
PS2_BA + 0x00
Descriptions
Reserved
FPS2DAT
FPS2CLK
OVERRIDE
CLRFIFO
ACK
30
22
14
6
Reserved
R/W
R/W
Reserved
Force PS2DATA Line
It forces PS2DATA high or low regardless of the internal state of the device controller if
OVERRIDE is set to high.
1 = Force PS2DATA high
0 = Force PS2DATA low
Force PS2CLK Line
It forces PS2CLK line high or low regardless of the internal state of the device
controller if OVERRIDE is set to high.
1 = Force PS2DATA line high
0 = Force PS2DATA line low
Software Override PS2 CLK/DATA Pin State
1 = PS2CLK and PS2DATA pins are controlled by S/W
0 = PS2CLK and PS2DATA pins are controlled by internal state machine.
Clear TX FIFO
Write 1 to this bit to terminate device to host transmission. The TXEMPTY bit in
PS2STATUS bit will be set to 1 and pointer BYTEIDEX is reset to 0 regardless there is
residue data in buffer or not. The buffer content is not been cleared.
1 = Clear FIFO
0 = Not active
Acknowledge Enable
1 = If parity error or stop bit is not received correctly, acknowledge bit will not be sent to
29
21
13
TXFIFO_DEPTH
5
Description
PS2 Control Register
28
20
12
4
- 461 -
Reserved
Reserved
FPS2DAT
27
19
11
3
Publication Release Date: Oct 22, 2010
FPS2CLK
RXINTEN
26
18
10
2
OVERRIDE
TXINTEN
25
17
9
1
Revision V1.06
Reset Value
0x0000_0000
CLRFIFO
PS2EN
24
16
8
0