NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 497

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

A/D Control Register (ADCR)
Register
ADCR
Bits
[31]
[30:12]
[11]
DMOF
31
23
15
7
TRGCOND
NuMicro™ NUC100 Series Technical Reference Manual
Offset
ADC_BA+0x20
Descriptions
DMOF
Reserved
ADST
30
22
14
6
Reserved
R/W
R/W
A/D differential input Mode Output Format (This bit is only support in Low Density)
1 = A/D Conversion result will be filled in RSLT at ADDRx registers with 2'complement
0 = A/D Conversion result will be filled in RSLT at ADDRx registers with unsigned
Reserved
A/D Conversion Start
1 = Conversion start
0 = Conversion stopped and A/D converter enter idle state
ADST bit can be set to 1 from two sources: software write and external pin STADC.
ADST is cleared to 0 by hardware automatically at the ends of single mode and single-
cycle scan mode on specified channels. In continuous scan mode, A/D conversion is
continuously performed sequentially until software write 0 to this bit or chip reset.
29
21
13
5
format.
format.
Description
ADC Control Register
TRGS
28
20
12
4
- 497 -
Reserved
Reserved
ADST
27
19
11
3
Publication Release Date: Oct 22, 2010
ADMD
DIFFEN
26
18
10
2
PTEN
ADIE
25
17
9
1
Revision V1.06
Reset Value
0x0000_0000
TRGEN
ADEN
24
16
8
0