NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 519

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.18.5 Register Map
R : read only, W : write only, R/W : both read and write
Register
PDMA_BA_ch0 = 0x5000_8000
PDMA_BA_ch3 = 0x5000_8300
PDMA_BA_ch6 = 0x5000_8600
PDMA_CSRx
PDMA_SARx
PDMA_DARx
PDMA_BCRx
PDMA_POINTx
PDMA_CSARx
PDMA_CDARx
PDMA_CBCRx
PDMA_IERx
PDMA_ISRx
PDMA_SBUF0_cx PDMA_BA_chx+0x80
PDMA_BA_GCR = 0x5000_8F00
PDMA_GCRCSR
PDMA_PDSSR0
PDMA_PDSSR1
PDMA_GCRISR
PDMA_PDSSR2
Notice: Low Density only support PDMA channel 0.
NuMicro™ NUC100 Series Technical Reference Manual
Offset
PDMA_BA_chx+0x00
PDMA_BA_chx+0x04
PDMA_BA_chx+0x08
PDMA_BA_chx+0x0C
PDMA_BA_chx+0x10
PDMA_BA_chx+0x14
PDMA_BA_chx+0x18
PDMA_BA_chx+0x1C
PDMA_BA_chx+0x20
PDMA_BA_chx+0x24
PDMA_BA_GCR+0x00 R/W
PDMA_BA_GCR+0x04 R/W
PDMA_BA_GCR+0x08 R/W
PDMA_BA_GCR+0x0C R/W
PDMA_BA_GCR+0x10 R/W
PDMA_BA_ch1 = 0x5000_8100
PDMA_BA_ch4 = 0x5000_8400
PDMA_BA_ch7 = 0x5000_8700
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R/W
R/W
R
Description
PDMA Control Register
PDMA Source Address Register
PDMA Destination Address Register
PDMA Transfer Byte Count Register
PDMA Internal buffer pointer
PDMA Current Source Address Register
PDMA Current Destination Address Register
PDMA Current Transfer Byte Count Register
PDMA Interrupt Enable Register
PDMA Interrupt Status Register
PDMA Shared Buffer FIFO 0
PDMA Global Control Register
PDMA Service Selection Control Register 0
PDMA Service Selection Control Register 1
PDMA Global Interrupt Register
PDMA Service Selection Control Register 2
- 519 -
Publication Release Date: Oct 22, 2010
PDMA_BA_ch2 = 0x5000_8200
PDMA_BA_ch5 = 0x5000_8500
PDMA_BA_ch8 = 0x5000_8800
Revision V1.06
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0001
0x0000_0000
0x0000_0000
0XFFFF_FFFF
Reset Value
0x0000_0000
0x0000_0000
0xXXXX_0000
0x0000_0000
0xFFFF_FFFF
0x0000_0000
0x0000_00FF